Tektronix WFM 601A, Service Manual

Page: 60 / 368

Block Diagram Descriptions
WFM 601A, WFM 601E, & WFM 601M Service Manual
3–5
transcoded GBR or component video channels (Y/P
b
/P
r
). Composite sync,
generated by the coprocessor, is added to the G/Y channel of the Monitor Out.
The Y/G, P
b
/B, and P
r
/R output impedance is set to 75
W .
The transcoded GBR signals drive the GBR to Diamond Transcoder. The outputs
from the transcoder are B+G and B–G for the top half of the Diamond display,
and R+G and R–G for the bottom half of Diamond display. Display mode
switching provides the vertical and horizontal axes inputs for Lightning,
Diamond, Component Vector, and Bowtie displays. The microprocessor controls
the display switching through the Controller circuit.
Block Diagram 3, Microprocessor and Control
The microprocessor has a 32 bit internal architecture and a 16-bit data bus. At
boot up it reads initial code from the Read-Only Memory (ROM). The micropro-
cessor then loads program code from EPROM into the RAM for execution. The
Nonvolatile Random Access Memory (NVRAM) stores all the calibration and
other constants used by the microprocessor.
The 24 bit Address Buffer is unidirectional and is used to select the addresses in
the storage devices (RAM, ROM, and EPROM). The Data Buffer is bidirection-
al. The flash EPROM is programmed through the RS-232 port.
The Line Rate Controller (LRC) is a custom IC that loads information from
ROM at power up. The microprocessor controls the LRC by placing commands
in the FIFO which the LRC reads. The LRC uses three clock inputs (5.5, 6, and
16 MHz) and the H sync pulse to synchronize to the incoming video reference
and to generate synchronous switching signals required to drive the various
displays modes.
The Sync Separator strips the sync pulses from either the internal video signal or
the external reference video. It generates H sync and V sync to synchronize the
Line Rate Controller.
Data and control signals from the microprocessor are loaded into latches clocked
by the Line Rate Controller, which lock their outputs to the incoming video
signal.
The Readout State Machine interprets the readout instructions from the micro-
processor and loads digital data into two identical DACs. The DACs drive the
vertical and horizontal stroke generators to create the readouts displayed on the
CRT.
GBR to Diamond
Transcoder and
Component Display
Switching
Microprocessor
Line Rate Controller
and FIFO
Sync Separator
Synchronous Outputs
Readout State Machine