Tektronix TMS 440 SH-3 7708, Instruction Manual

Page: 48 / 100

Setting Up the Support
2–8
TMS 440 SH-3 7708 Microprocessor Support
CKIO
L_BS~
Data
M ;
Address A25-A0
DL_RASD~
Row Address
Data
DL_WER~
(Asserted for Write)
A ; D ; C ;
RD/WR~
DL_CASD~
(Asserted for Read)
Figure 2–6: PSRAM Access bus timing
SDRAM Mode Register Accesses. SDRAM Mode Register Accesses are handled
by the SDRAM/NORMAL clocking options. This access is marked mainly by
L_RAS~ and L_CAS~ signals both going low together which does not happen
for normal or burst in Read or Write Cycle types. When L_RAS~ AND L_CAS~
are both low at a rising CKIO edge, the Address, Data, and Control signals are
logged-in and mastered see Figure 2–7.