Tektronix TMS 440 SH-3 7708, Instruction Manual

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Setting Up the Support
TMS 440 SH-3 7708 Microprocessor Support
2–5
EDO DRAM. EDO DRAM accesses are handled by EDODRAM/NORMAL or
A2–DRAM/A3–EDODRAM/NORMAL clocking options. The Address, Data
and Control signals are logged-in every rising CKIO edge after the DL_CASD~
qualifier is low. In the next trailing edge of CKIO, if DL_CASD~ is high, it is
mastered, if DL_CASD~ is low Address, Data, and Control signals are logged-in
the next rising edge of CKIO. The DL_CASD~ for these cycles will go from
low to high after a trailing edge of CKIO before the rising edge of CKIO see
Figure 2–3.
CKIO
DL_CASD~
Data
A ;
M ;
Address A25 - A16
DL_RASD~
Address A15 - A0
RD/WR~
Row address
Data
Row address
Column address
L_RAS~
L_BS~
D ; C;
Figure 2–3: EDO DRAM Access bus timing
SDRAM Read. SDRAM accesses are handled by the SDRAM/NORMAL clocking
options. The Row Address and Control signals are logged-in and mastered at the
rising CKIO edge if the L_RAS~ is low and if DL_CASD~ and L_CAS~ is high
see Figure 2–4.
In the coming rising edges of CKIO:
a. If the L_CAS~ is low, the Column Address and Control signals are
logged-in and mastered.