Tektronix TLA600 Series, Service Manual

Page: 26 / 188

Specifications
TLA600 Series Logic Analyzer Service Manual
1- 3
Table 1- 2: TLA600 timing latencies (Cont.)
Characteristic Description
OR function 366 ns + SMPL
AND function 379 ns + SMPL
LA Probe Tip to External Signal Out via
Signal 1, 2
4, 5
normal function 364 ns + SMPL
inverted logic on backplane 364 ns + SMPL
1
All system trigger and external signal input latencies are measured from a falling-edge transition (active true low) with
signals measured in the wired-OR configuration.
2
In the Waveform window, triggers are always marked immediately except when delayed to the first sample. In the Listing
window, triggers are always marked on the next sample period following their occurrence.
3
“Clk” represents the time to the next master clock at the destination logic analyzer. In the asynchronous (or internal)
clock mode, this represents the delta time to the next sample clock beyond the minimum asynchronous rate of 4 ns. In
the synchronous (or external) clock mode, this represents the time to the next master clock generated by the setup of the
clocking state machine and the supplied system under test clocks and qualification data.
4
Signals 1 and 2 (ECLTRG0, 1) are limited to a “broadcast” mode of operation, where only one source is allowed to drive
the signal node at any one time. That single source may be utilized to drive any combination of destinations.
5
SMPL represents the time from the event at the probe tip inputs to the next valid data sample. In the Normal Internal clock
mode, this represents the delta time to the next sample clock. In the MagniVu Internal clock mode, this represents 500 ps
or less. In the External clock mode, this represents the time to the next master clock generated by the setup of the
clocking state machine, the system-under-test supplied clocks, and the qualification data.
Table 1- 3: TLA600 external signal interface
Characteristic Description
System Trigger Input TTL compatible input via rear panel mounted BNC connectors
Input Levels
V
IH
V
IL
TTL compatible input.
≥
2.0 V
≤
0.8 V
Input Mode Falling edge sensitive, latched (active low)
Minimum Pulse Width 12 ns
Active Period Accepts system triggers during valid acquisition periods via real-time gating, resets system
trigger input latch between valid acquisition periods
Maximum Input Voltage 0 to +5 V peak
External Signal Input TTL compatible input via rear panel mounted BNC connectors
Input Destination Signal 1, 2, 3, 4
Input Levels
V
IH
V
IL
TTL compatible input.
≥
2.0 V
≤
0.8 V