Tektronix MTS415, Technical Reference

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Specifications
Version 00b
MTS400 Series Performance Verification and Specifications Technical Reference
1−7
Table 1−3: A170 LVDS/ASI/SMPTE310M Interface card electrical
characteristics (Cont.)
Characteristic Description
Output
Output impedance 75 transformer coupled
Voltage 800 mV
"
10% into 75 load
Jitter, typical <2 ns p-p logic 0 rising edge when triggered on
negative edge (EN50083-9.1998 Figure A.4)
<1.4 ns p-p logic 1 rising edge when triggered on
negative edge (EN50083-9.1998 Figure A.5)
Rise/fall time 0.4 ns
v
X
v
5 ns, 20% to 80%
Return loss, typical >30 dB (5 MHz to 38.785316 MHz) into 75 load
SMPTE310M interface (cont.)
Input
Input impedance 75 transformer coupled
Voltage 200 mV to 880 mV (maximum limit: 3 V
pp
@AC,
15 mA @DC)
Data format Bi-phase coded, compliant with SMPTE310M
Input bit rate 19,392,658.5 bps
Return loss, typical >17 dB (5 MHz to 38.785316 MHz) into 75 load
DVB−SPI interface
Input/output configuration Input only
Connector type D-sub, 25-pin
Data rate 250 kbps to 108 Mbps (107 Mbps maximum in
duplex mode)
Pin assignment 1 DCLK
2 Ground
3 to 10 DATA 7 to DATA 0
11 DVALID
12 PSYNC
13 Shield
14 /DCLK
15 Ground
16 to 23 /DATA 7 to DATA 0
24 /DVALID
25 /PSYNC
Data delay
"
5 ns from DCLK falling edge
Input level >200 mVpp, (RI+)−(RI−) with 100 termination
Input impedance 100 , between differential inputs
Clock pulse width T/2
"
T/10, T=1/f (f = byte clock frequency)
Data hold time T/2
"
T/10, T=1/f, data latch on DCLK rising edge