GTS1063 and GTS1250 GBIC Test Systems Instruction Manual
29
Specifications
This section contains the specifications of the GTS1250 and GTS1063 GBIC
Test Systems. All specifications are guaranteed unless noted as “typical.” Typical
specifications are provided for your convenience but are not guaranteed.
Specifications marked with the
n
symbol have corresponding checks in the
Performance Verification section on page 43.
Table 6: Tx Data and Tx Clock Out Specifications
Specification
Description
Tx Data rate (Clk frequency)
Tx output data rate (internally generated patterns):
GTS1250:
1.250000 Gb/s
"
75 ppm
GTS1063:
1.06250000 Gb/s
"
75 ppm
Test Method: The Tx pattern is set to K28.7 (5 1s, 5 0s) such that the output is a
125 MHz (GTS1250) or 106.25 MHz (GTS1063) square wave; the Tx DATA electrical
output is sent to a counter capable of measuring past 125 MHz.
Tx Rise and fall times
CLK and DATA output rise time:
t
300 ps
CLK and DATA output fall time:
t
300 ps
Rise and fall times are the transition duration from 10% to 90% (rise) or
90% to 10% (fall). A 50
output termination is required to meet specification.
n
Tx Output level swings
Output swing levels are specified for 50
RF cable lengths of
t
0.5 m in length and
t
0.25 dB loss in the first 2 GHz frequency range.
Tx DATA output peak-to-peak
minimum:
u
300 mV
p-p
maximum:
t
600 mV
p-p
Tx CLK output peak-to-peak
minimum:
u
300 mV
p-p
maximum:
t
600 mV
p-p
Both the Tx DATA and CLK outputs are AC coupled and require external 50
termination for proper output swings. The 50
cable (Tektronix part number
015-0560-00) used is relatively short (2 ns).
Tx SYNC output peak-to-peak
minimum:
u
300 mV
p-p
maximum:
t
600 mV
p-p
The SYNC Out pulse is AC coupled and requires external 50
termination for proper
output swings. The level of the Sync Out pulse relative to AC-GND level depends on the
duty cycle of the SYNC Out pulse; this is pattern dependent. The 50
cable (Tektronix
part number 015-0560-00) used is relatively short (2 ns).
n
Tx Data, Data duty cycle (balance)
Tx DATA signals have a balanced output of 50%
"
1% for internally generated data
patterns only.
For a pattern with a perfect balance between numbers of logical 1s and 0s, the Tx Data
output shall individually have a balanced 50% duty cycle output.
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