Supero SUPER P4SDA+, User Manual

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Chapter 1: Introduction
1-13
1-2 Chipset Overview
Intel’s 845 chipset is made up of three main components:
The 82845 Memory Controller Hub (MCH) with an Accelerated Hub Architec-
ture (AHA) bus, the 82801 BA I/O Controller Hub (ICH2) with an AHA bus
and the 82802 AB Firmware Hub (FWH).
Memory Controller Hub (MCH)
The MCH includes the host (CPU) interface, memory interface, ICH2 inter-
face and 4xAGP interface for the 845 chipset. It contains advanced power
management logic and supports three DIMMS for up to 2 GB of unbuffered
DDR RAM. The AGP 2.0 interface supports 4x data transfers and operates
at a peak bandwidth of 1056 GB. The MCH host (front side bus) interface
bus runs at 400 MHz.
I/O Controller Hub (ICH2)
The ICH2 is the I/O Controller Hub subsystem on the P4SDA/P4SDM, which
integrates many of the input/output functions of the 845 chipset, including a
two-channel ATA100 Bus Master IDE controller. It also provides the inter-
face to the PCI Bus and communicates with the MCH over a dedicated hub
interface bus -- the AHA. The P4SDA+/P4SDM features the ICH2, which
includes a dual channel IDE controller plus two USB controllers that offer 24
Mbps of bandwidth across four ports. ICH2 also features an enhanced
AC97 interface that supports full surround sound for the Dolby Digital Audio
used on DVDs.
Firmware Hub (FWH)
The FWH is a component that brings added security and manageability to
the PC platform infrastructure. This device includes an integrated Random
Number Generator (RNG) for stronger encryption, digital signing and secu-
rity protocols. The FWH stores the system BIOS and video BIOS to eliminate
a redundant nonvolatile memory component.