Supermicro X5DPL-TGM, User Manual

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Chapter 1: Introduction
1-11
Introduction
• PCI 2.2 Compliant 32/64-bit bus, up to 66 MHz
• PCI-X Rev. 1.0 Compliant 32/64-bit bus, up to 133MHz
• Supports 64-bit addressing via Dual Address Cycle (DAC) Transactions
• Compliant with PCI Power Management (PMG)
Features
• Supports up to two outstanding delayed read transactions (PCI 2.2)
• Supports up to four split transactions (PCI-X)
• Supports UP TO 4 MB expansion ROM for add-in cards
• Serial EPROM initialization interface
• Enhanced-DMA (EDMA) per SATA port
• Automatic command execution without host intervention
• 64-bit addressing support for descriptions and data buffers in system
memory
• 512-byte buffer for read and write transactions per SATA port
• Read ahead
• Interrupt coalescing (one interrupt or less per I/o transaction)
64-bit PCI/PCI-X Interface
PCI/PCIX Interface
Serial
Initialization
Interface
Crossbar
Interface
Flash
Interface
SATA Controller 0
SATA Controller 1
Port0 Port1 Port2 Port3 Port4 Port5 Port6
Port7
Figure 1-6. Marvell 88SX5081Host Controller Block Diagram