SuperServer 7088B-TR4FT User's Manual
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Chipset Configuration
North Bridge
This feature is used to configure Intel North Bridge settings.
Integrated IO Configuration
EV DFX (Device Function On-Hide) Features
When this item is set to Enable, the EV_DFX Lock Bits that are located on a processor
will always remain clear during electric tuning. The options are
Disable
and Enable.
IIO0 Configuration/IIO1 Configuration/IIO2 Configuration /IIO3
Configuration/IIO4 Configuration/IIO5 Configuration/IIO6 Configuration /
IIO7 Configuration
PCI Express Port 0 (DMI)
Use the items below to configure the PCI-E settings for a PCI-E port specified by the
user. The following items will display:
•
PCI-E Port Link Status
•
PCI-E Port Link Max
•
PCI-E Port Link Speed
Link Speed
Use this item to select the PCI-E link speed for the PCI-E port specified by the user. The
options for CPU-PCH DMI port are
Auto
, GEN1 (2.5 GT/s), and GEN2 (5 GT/s). The op-
tions for Onboard LAN are Auto, GEN1 (2.5 GT/s),
GEN2 (5 GT/s)
, and GEN3 (8 GT/s).
The options for CPU1 Slot1 X8 are
Auto
, GEN1 (2.5 GT/s), GEN2 (5 GT/s), and GEN3
(8 GT/s). CPU1 Slot2 X16 port are
Auto
, GEN1 (2.5 GT/s), GEN2 (5 GT/s), .and GEN3
(8 GT/s). (Note: the option of GEN3 (8 GT/s) is available on the IIO4 Configuration/IIO5
Configuration/IIO6 Configuration /IIO7 Configuration only.)
PCI Express Port 1A/PCI Express Port 1B/PCI Express Port 2A/PCI
Express Port 2B/PCI Express Port 2C/PCI Express Port 2D/PCI Express
Port 3A/PCI Express Port 3B/PCI Express Port 3C/PCI Express Port 3D
Use the items below to configure the PCI-E settings for a PCI-E port specified by the
user. The following items will display:
•
PCI-E Port Link Status
