Struck SIS3800, User Manual

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SIS Documentation SIS3800
Scaler/Counter
Page 13 of 39
7.3 Address Map
The SIS360x/38xx boards are operated via VME registers, VME key addresses and the FIFO
(where installed). The following table gives an overview on all SIS3800 addresses and their
offset from the base address, a closer description of the registers and their function is given in
the following subsections.
Offset Key Access Type Function
0x000 R/W D16/D32 Control and Status register
0x004 R/W D16/D32 Module Identification and IRQ control register
0x00C W D16/D32 Selective count disable register
0x020 KA W D16/D32 clear all counters and overflow bits
0x024 KA W D16/D32 clock shadow register
0x028 KA W D16/D32 global count enable
0x02C KA W D16/D32 global count disable
0x030 KA W D16/D32 Broadcast; clear all counters and overflow bits
0x034 KA W D16/D32 Broadcast; clock shadow register
0x038 KA W D16/D32 Broadcast; global count enable
0x03C KA W D16/D32 Broadcast; global count disable
0x040 KA W D16/D32 clear counter group and overflow channel 1-8
0x044 KA W D16/D32 clear counter group and overflow channel 9-16
0x048 KA W D16/D32 clear counter group and overflow channel 17-24
0x04C KA W D16/D32 clear counter group and overflow channel 25-32
0x050 KA W D16/D32 enable reference pulser channel 1
0x054 KA W D16/D32 disable reference pulser chanel 1
0x060 KA W D16/D32 reset register (global reset)
0x068 KA W D16/D32 Test pulse (generate a single pulse)
0x100-
0x17C KA W D16/D32 clear counter N and its overflow bit
0x180-
0x1FC KA W D16/D32 clear overflow bit of counter N
0x200-
0x27C R D16/D32/
BLT32 read shadow register (does not initiate clock shadow)
0x280-
0x2FC R D16/D32/
BLT32 read counter (initiates clock shadow also)
0x300-
0x37C R D16/D32/
BLT32 read and clear all counters
0x380 R D16/D32 Overflow register channel 1-8
0x3A0 R D16/D32 Overflow register channel 9-16
0x3C0 R D16/D32 Overflow register channel 17-24
0x3E0 R D16/D32 Overflow register channel 25-32
Note: D08 is not supported by the SIS38xx boards
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