SIS Documentation
SIS3800
Scaler/Counter
Page 20 of 39
10 Data Format
The data format of the actual counter values (read via the shadow register) for D16 and D32
reads is shown in the two tables below.
10.1 D16
high Byte
low Byte
first read
Data Bits 31-24
Data Bits 23-16
second read
Data Bits 15-8
Data Bits 7-0
10.2 D32
Data Bits 31-24
Data Bits 23-16
Data Bits 15-8
Data Bits 7-0
11 Readout Schemes
Scaler data can be read from different locations. The read location has an impact on the
counter behaviour.
11.1 Read Shadow Register
In a single cycle or block transfer read from the shadow register (0x200-0x27C) the data from
the last transfer to the shadow register are obtained. No automatic clock shadow is initiated,
i.e. if the user wants to read the actual scaler values he has to ensure a soft- or hardware clock
shadow before the read.
11.2 Read and Clear all Counters
In a single cycle or block read from the read and clear all counter registers (0x300-0x37C) the
data are transferred into the shadow register, all counters are cleared after the transfer and the
shadow data are read.
Note: If your CPU does not support block transfer you can ensure synchronicity to 5 ns
by reading the first scaler value from 0x300 and the rest from the shadow registers
0x204-0x27C.
11.3 Read Counter
The read counter behaves like the read and clear all counters except that the counter values
are not cleared after the copy to the shadow register.
11.4 Special behaviour of Firmware Version 3
Firmware Version 3 differs from Versions 1 and 2 with respect to the read on the fly
behaviour. To avoid the 6-bit read on the fly uncertainty the clock shadow register transaction
is combined with a count inhibit of about 200 ns of all channels. This results in an accurate
counter result, but at the cost of an overall deadtime. It will depend on the given application,
whether this mode is an attractive option.
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