Stageline SP218UXL, Description

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SP218UXL-19“
39
7.1 DMX512 Timing Diagramm
Packet (22,7ms)
= Break + MAB + Start byte + data packet with
up to 512 bytes
Inter-Packet time = Time between two frames
Slot (44µs)
= 1 Start bit, Data byte (8Bit), 2 Stop bits
Inter-Slot time = Time between two data bytes
7.2 RETIMER preset Table
BREAK MAB DATA MBB Beschreibung Anzeige
(µs) (µs) (µs) (µs)
176 12
44
0 B2B 22,8ms ! 44u
176 12
48
0 48 µs per byte 48u
176 12
48
176 48 µs & MBB 176 µs 48U
176 12
52
0 52 µs 52u
176 18
52
176 52 µs & MBB 176 µs 52U
176 18
56
0 56 µs 56u
176 18
56
352 56 µs & MBB 352 µs 56U
176 18
60
0 60 µs 60u
176 18
60
352 60 µs & MBB 352 µs 60U
176 18
64
0 64 µs 64u
176 18
64
352 64 µs & MBB 352 µs 64U
176 18
72
0 72 µs 72u
176 18
72
352 72 µs & MBB 352 µs 72U
179 22 64 352 64 µs & MBB 352 µs 30F
(
30
frames / second)