•
A data group/lane which contains 8 signals.
Note:
It depends of the memory specification: SDRAM with x8 bus widths have only one data group, while x16 bus-
width SDRAM have two lanes.
Interface signal layout guidelines
•
For reference the plane using GND or PWR (if PWR), add 10 nf stitching cap between PWR and GND.
•
Trace impedance: 50 Ω ± 10%.
•
The maximum trace length should not exceed 120mm. If the signal trace exceeds this trace-length / speed
criteria, then a termination should be used.
•
To reduce the crosstalk, it is strongly recommended to place data tracks on the different layers to the
address and control lanes. However, when the data and address / control tracks coexist on the same layer
they must be separated from each other by at least 5 mm.
•
Match the trace lengths for the data group within ± 10 mm of each other to reduce any excessive skew.
Serpentine traces (this is an “S” pattern to increase trace length) can be used to match the lengths.
•
Placing the clock (SDCLK) signal on an internal layer, minimizes the noise (EMI). Route the clock signal at
least three times the width of the trace away from others signals. To avoid unnecessary impedance changes
and reflection, avoid the use of vias as much as possible. Serpentine routing is to be avoided also.
•
Match the clock traces to the data/address group traces length to within ±10 mm.
•
Match the clock traces length to each signal trace in the address and command groups to within ±10 mm
(with maximum of ≤ 20 mm).
•
Trace capacitances:
–
At 3.3 V keep the trace capacitance within 20 pF with overall capacitive loading (including Data,
Address, SDCLK and Control) no more than 30 pF.
–
At 1.8 V keep the trace capacitance within 15 pF with overall capacitive loading (including Data,
Address, SDCLK and Control) no more than 20 pF.
9.4.3
Octo-SPI interface
Interface connectivity
The Octo-SPI is a specialized communication interface targeting single, dual, quad and octal communication.
(Refer to the reference manual
STM32H723/733, STM32H725/735 and STM32H730 advanced Arm
®
-based 32-
bit MCUs
(RM0468)) for details)
Refer to the
STM32H72x and STM32H73x datasheets
for the full electrical characteristic.
Interface signal layout guidelines
•
Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR and GND
•
Trace impedance: 50 Ω for single-ended and 100 Ω for differential pairs (CLK/NCLK)
•
The maximum trace length should be less than120 mm. If the signal trace exceeds this trace-length/speed
criterion, then a termination should be used
•
Avoid using multiple signal layers for the data signal routing.
•
Route the clock signal at least three times the width of the trace away from other signals. To avoid
unnecessary impedance changes and reflection, avoid the use of vias as much as possible. Serpentine
routing is to be avoided also.
•
Match the trace lengths for the data group within ± 10 mm of each other to reduce any excessive skew.
Serpentine traces (this is an “S” shape pattern to increase trace length) can be used to match the lengths.
•
Avoid using a serpentine routing for the clock signal and use via(s) as little as possible for the whole path. A
via alters the impedance and adds a reflection to the signal.
•
Avoid discontinuities on high speed traces (vias, SMD components).
Figure 23. Octo-SPI interconnection example
Figure 24. Octo-SPI multiplexed interconnection example
illustrate possible interconnection examples.
If SMD components are needed, place these components symmetrically to ensure good signal quality.
AN5419
High speed signal layout
AN5419
-
Rev 2
page 38/50