ST STM32H723, Getting Started, Page: 31 / 50

7 Recommendations
7.1 Printed circuit board
For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to
the ground (V
SS
) and another dedicated to the V
DD
supply. This provides both good decoupling and good
shielding effect. For many applications, cost reasons prohibit the use of this type of board. In this case, the major
requirement is to ensure a good structure for the ground and the power supply.
7.2 Component position
A preliminary layout of the PCB must separate the different circuits according to their EMI contribution in order to
reduce the cross-coupling on the PCB, that is noisy, high-current circuits, low-voltage circuits, and digital
components.
7.3 Ground and power supply (V
SS
,V
DD
)
Every block (noisy, low-level sensitive, digital, etc.) should be grounded individually and all ground returns should
be to a single point. Loops must be avoided or have a minimum area. The power supply should be implemented
close to the ground line to minimize the supply loop area. This is due to the fact that the supply loop acts as an
antenna, and therefore will become the EMI main transmitter and receiver. All component-free PCB areas must
be filled with additional grounding to create adequate shielding (especially when using single-layer PCBs).
7.4 Decoupling
All the power supply and ground pins must be properly connected to the power supplies. These connections,
including pads, tracks and vias should have lowest possible impedance. This is typically achieved with thick track
widths and, preferably, the use of dedicated power supply planes in multilayer PCBs.
In addition, each power supply pair should be decoupled with filtering ceramic capacitors (100 nF) and one single
ceramic capacitor (min. 4.7 μF) connected in parallel. These capacitors need to be placed as close as possible to,
or below, the appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF, but the exact
values depends on the application needs.
Figure 16. Typical layout for V
DD
/V
SS
pair shows the typical layout of
such a V
DD
/V
SS
pair.
Figure 16. Typical layout for V
DD
/V
SS
pair
Via to VDD Via to VSS
VDD VSS
Cap.
STM32H7xx
Cap.
AN5419
Recommendations
AN5419 - Rev 2
page 31/50