6.3.3
Internal pull-up and pull-down on JTAG pins
The devices embed internal pull-ups and pull-downs to guarantee a correct JTAG behavior. Consequently, the
pins are not left floating during reset and they are configured as follows until the user software takes control of
them:
•
NJTRST: internal pull-up.
•
JTDI: internal pull-up.
•
JTMS/SWDIO: internal pull-up.
•
JTCK/SWCLK: internal pull-down.
•
JTDO: floating state (tristate)
If these I/Os are externally connected to a different voltage, a leakage current will flow during and after reset, until
they are reconfigured by software. Special care must be taken with the TCK/SWCLK pin, which is directly
connected to some of the clock flip-flops, since it should not toggle before JTAG I/O is released by the user
software.
6.3.4
SWJ debug port connection with standard JTAG connector
Figure 15. JTAG connector implementation
shows the connection between STM32H723/33, STM32H725/35 and
STM32H730 microcontrollers and a standard JTAG connector.
Figure 15.
JTAG connector implementation
V
DD
STM32Hxxx
nJTRST
JTDI
JSTM/SWDIO
JTCK/SWCLK
JTDO
nRSTIN
(1) VTREF
(3) nTRST
(5) TDI
(7) TMS
(9) TCK
(11)RTCK
(13)TDO
(15)nSRST
(17)DBGRQ
(19)DBGACK
10 kΩ
10 kΩ
10 kΩ
(2)
(4)
(6)
(8)
(10)
(12)
(14)
(16)
(18)
(20)
Connector 2x10
JTAG connector CN9
V
DD
V
SS
AN5419
Pinout and debug port pins
AN5419
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Rev 2
page 30/50