Board architecture
UM0522
18/39
Figure 10.
Board schematic - power block
R2
5
100K -1/2W
1
2
3
Q
7
STD
5NK
5
2ZD
-1
HV Mo
ni
tori
n
g
BE
2
1
2
3
Q
8
STD
5NK
5
2ZD
-1
1
2
3
Q
9
STD
5NK
5
2ZD
-1
BF
2
1
2
3
Q
1
0
STD
5NK
5
2ZD
-1
1
2
3
Q
1
1
STD
5NK
5
2ZD
-1
1
2
3
Q
1
2
STD
5NK
5
2ZD
-1
P
ha
se
C
P
ha
se
B
P
ha
se
A
R2 68
0
K
R2
5
100K -1/2W
1
2
3
Q
7
STD
5NK
5
2ZD
-1
HV Mo
ni
tori
n
g
BE
2
1
2
3
Q
8
STD
5NK
5
2ZD
-1
1
2
3
Q
9
STD
5NK
5
2ZD
-1
BF
2
1
2
3
Q
1
0
STD
5NK
5
2ZD
-1
1
2
3
Q
1
1
STD
5NK
5
2ZD
-1
1
2
3
Q
1
2
STD
5NK
5
2ZD
-1
P
ha
se
C
P
ha
se
B
P
ha
se
A
R2 68
0
K
R4
1
2
K
C6
1
uF
/1
6V
1
6
V
G
ND
B
D
1
TR1
tra
ns
il
1
2
3
J8
CO
N
3
G
ND
B
F
1
+
5V
BA
1
+15
V
120
/2
30
-
V
ac
1
2
D6
BZX
8
5C
1
6
1
2
D5
BZX
8
5C
5
V
1
1
2
D1
9
STTH
1
0
6
1
2
D1
8
STTH
1
0
6
1
2
D2
0
STTH
1
0
6
C2
2
.2
uF/
2
5
V
C4
2
2
nF
/5
0V
R2
4
100K -1/2W
C1
BE
1
15
-
5A
R6
4
1
.2K
R6
5
1
.2K
R6
6
1
.2K
Neu
tra
l
-M
ain
Pha
se
-M
ain
+15
V
1
2
J9
2
3
0
VAC
1
2
CO
N
2
+15
V
V
in
3
G
ND
2
V
o
ut
1
IC2
L
7
8
L
0
5
ACZ
L
SCS
1
2
D2
STTH
1
0
6
R1
0
0
.1R
-2
.5
W
-
+
D2
1
BRID
G
E
_
2K
P
B
**
C5
1
0
0
uF
/2
5V
C8
2
2
nF
/4
00
V
D7
STTH
1
0
8
t
NTC
R1
3
8
2
K
R1
2
8
2
K
R1
8
8
2
K
R1
7
8
2
K
R1
6
8
2
K
R1
5
8
2
K
C9
1
0
0
nF
/5
0V
1
2
D3
BZX
8
4C
1
5
D2
STTH
1
0
6
R1
0
0
.1R
-2
.5
W
-
+
D2
1
BRID
G
E
_
2K
P
B
**
C5
1
0
0
uF
/2
5V
C8
2
2
nF
/4
00
V
D7
STTH
1
0
8
t
NTC
R1
3
8
2
K
R1
2
8
2
K
R1
8
8
2
K
R1
7
8
2
K
R1
6
8
2
K
R1
5
8
2
K
C9
1
0
0
nF
/5
0V
1
2
D3
BZX
8
4C
1
5
L
1
1mH/
3
5
0mA
1
2
D1
1N
4
1
4
8
2
4
5
6
7
8
1
3
VDD
DRA
IN
SET
RES
-
+
0.2
3V
SO
U
RC
E
FB
IC1
VI
P
E
R
1
2
A
D
IP
Not mounted
T
OKO
00499
BE
MFC
GND
BB
1
BE
MFB
C3
1
0
uF
/3
5V
3
5
V
C1
0
CAP
NP
0
.2
2
uF
2
75
V
-X
2
F1
FUSE
3A
BE
MFA
BA
2
BC1
BB
2
BC2
R3
3
3
0
K
BD2
2
2
0
uF
/4
50V
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