PulseBlasterESR-PRO
Specifications
TTL Specifications
21 individually controlled digital output lines (LVTTL levels, 3.3 V logical “one” unterminated)
4 bracket mounted BNC connectors, impedance matched to 50 ohm, for board
24 BNC connectors for rackmount system, 21 of which are independently controlled output
channels
Variable pulses/delays for every TTL line
25 mA output current per TTL line
Pulse Parameters (using 500 MHz clock frequency)
2 ns shortest pulse
10 ns shortest interval
1
104 days longest pulse/interval (using the long delay instruction)
2 ns pulse/interval resolution
4096 instructions
External triggering and reset – 3.3V LVTTL levels
Pulse Program Control Flow (Common)
Loops, nested 8 levels deep
20 bit loop counters (max. 1,048,576 repetitions)
Subroutines, nested 8 levels deep
Wait for trigger – 8 clock cycle latency (16ns at 500 MHz), adjustable to 0.89 seconds in duration
15 MHz max. re-triggering frequency
1
NOTE: For PulseBlasterESR-PRO-500 design 17-11, instructions with CONTINE, JSR, RTS and LONG_DELAY OpCodes, require a
minimum instruction time of at least 6 clock-cycles (12.0 ns). For PulseBlasterESR-PRO-400 design 9-18, the minimum instruction time
is 7 clock-cycles (17.5 ns).
2019/09/26
