51
Pin No.
132
133, 134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172 to 176
Pin Name
FDO
GNDA2, GNDA1
SPO
VC2
MDIN2
MDIN1
VCCA1
CLVS
VSS
MDSOUT
VDD
MDPOUT
DEFECT
GSCOR
EXCK
SBIN
VSS
SCOR
WFCK
VDD5V
XRCI
VDDS
C2PO
VDD
DBCK
BCLK
DDAT
MDAT
VSS
DLRC
LRCK
XRST
IFS0
IFS1
XTAL
VSS
XTA2
XTA1
VDD
D0 to D4
I/O
O
—
O
I
I
I
—
O
—
O
—
O
I
I
O
I
—
I
I
—
I
—
I
—
O
I
O
I
—
O
I
I
I
I
I
—
O
I
—
I/O
Description
Signal output from the charge pump for frequency comparator
Ground terminal (analog system)
Spindle motor (M3) control signal output to the BA5912AFP (IC512)
Middle point voltage (+1.65V) input terminal
Spindle motor (M3) control signal input from the CXD3008Q (IC509)
MDP input terminal
Power supply terminal (+3.3V) (analog system)
Control signal output for selection the spindle control filter at CLVS
Ground terminal (digital system)
Frequency error output terminal of internal CLV circuit
Power supply terminal (+3.3V) (digital system)
Phase error output terminal of internal CLV circuit
Defect signal input terminal Not used (fixed at “L” )
Guard subcode sync OR signal input from the CXD3008Q (IC509)
Subcode serial data reading clock signal output to the CXD3008Q (IC509)
Subcode serial data input from the CXD3008Q (IC509)
Ground terminal (digital system)
Subcode sync OR signal input from the CXD3008Q (IC509)
Write frame clock signal input from the CXD3008Q (IC509)
Power supply terminal (+5V)
RAM overflow signal input terminal Not used (fixed at “L”)
Power supply terminal (+5V) (digital system)
C2 pointer signal input from the CXD3008Q (IC509)
Power supply terminal (+3.3V) (digital system)
Bit clock signal (2.8224 MHz) output terminal Not used (open)
Bit clock signal (2.8224 MHz) input from the CXD3008Q (IC509)
PCM data output terminal Not used (open)
Serial data input from the CXD3008Q (IC509)
Ground terminal (digital system)
L/R sampling clock signal (44.1 kHz) output terminal Not used (open)
L/R sampling clock signal (44.1 kHz) input from the CXD3008Q (IC509)
Reset signal input from the expander (IC902) “L”: reset
Interface select signal input terminal Fixed at “L” in this set
Interface select signal input terminal Fixed at “H” in this set
33.86688 MHz clock signal input terminal
Ground terminal (digital system)
System clock output terminal (33.86688 MHz)
System clock input terminal (33.86688 MHz)
Power supply terminal (+3.3V) (digital system)
Two-way data bus with the CPU (IC901) and expander (IC902)
Summary of Contents for SCD-C333ES - Super Audio Cd Changer
Page 18: ...SCD C333ES 18 18 4 2 SCHEMATIC DIAGRAM RF SECTION Refer to page 40 for Waveforms ...
Page 28: ...SCD C333ES 28 28 4 12 SCHEMATIC DIAGRAM AUDIO SECTION 2 3 ...
Page 29: ...SCD C333ES 29 29 4 13 SCHEMATIC DIAGRAM AUDIO SECTION 3 3 ...
Page 34: ...SCD C333ES 34 34 4 18 SCHEMATIC DIAGRAM HP SECTION ...
Page 36: ...SCD C333ES 36 36 4 20 SCHEMATIC DIAGRAM SENSOR SECTION Refer to page 45 for IC Block Diagram ...
Page 38: ...SCD C333ES 38 38 4 22 SCHEMATIC DIAGRAM POWER SECTION ...
