Sony NW-A1000, Service Manual

Page: 45 / 58

45
NW-A1000
Pin No. Pin Name I/O Description
89 SDATAO1 I
Audio data input from the main system controller
90 GNDIO1 -
Ground terminal (for I/O)
91 MULTI_SO I Serial data input from the main system controller
92 DEN_SI0 O
Serial data output to the sub system controller
93
WAKEUP_DEN
O
Wake-up signal output to the sub system controller
94 DEN_SERQ O Interrupt request signal output to the sub system controller
95 DEN_PCMDI O
Audio data output to the sub system controller
96 XRESET_DEN O
Reset signal output to the sub system controller "L": reset
97 VCCIO1 - Power supply terminal (+3V) (for I/O)
98 TDO O
Data output terminal (for JTAG) Not used
99 VCC -
Power supply terminal (+1.8V) (for core)
100 GND -
Ground terminal
101 DEN_BCK0 I
Bit clock signal input from the sub system controller
102 XINT_DEN I
Interrupt request signal input from the sub system controller
103 DEN_PCMD0 I
Audio data input from the sub system controller
104
DEN_DATA_RDY
I Ready signal input from the sub system controller
105 DEN_SCS0 I
Chip select signal input from the sub system controller
106 DEN_LRCK0 I
L/R sampling clock signal input from the sub system controller
107 GNDIO1 - Ground terminal (for I/O)
108 VCCIO1 -
Power supply terminal (+3V) (for I/O)
109 FRES_RXW I
Read/write control signal input from the main system controller
110 IIS_CLR_IN I IIS CLR control signal input terminal
111, 112
FRES_A3,
FRES_A2
I
Address signal input from the main system controller
113 FRES_XOE I
Read signal input from the main system controller
114 FRES_A1 I Address signal input from the main system controller
115
FRES_XCS1
I
Chip select signal input from the main system controller
116 FS256 I
11.2896 MHz clock signal input from the main system controller
117 VCC - Power supply terminal (+1.8V) (for core)
118 NC -
Not used
119 SCLK3 O
Bit clock signal output to the main system controller
120 DENDE_SS O Interrupt permission signal output to the main system controller
121 DATA_READY O
Ready signal output to the main system controller
122 SDATAI3 O
Audio data output to the main system controller
123 LRCK3 O L/R sampling clock signal output to the main system controller
124 XINT_DENDE O
Interrupt request signal output to the main system controller
125 VCCIO0 -
Power supply terminal (+3V) (for I/O)
126 GNDIO0 - Ground terminal (for I/O)
127 FRES_D27 I/O
Two-way data bus with the USB controller, main system controller, SD-RAM and NOR flash
memory
128 NC -
Not used
129 FRES_D26 I/O
Two-way data bus with the USB controller, main system controller, SD-RAM and NOR flash
memory
130 NC -
Not used
131, 132
FRES_D25,
FRES_D24
I/O
Two-way data bus with the USB controller, main system controller, SD-RAM and NOR flash
memory