Sony DWT-B30, Service Manual

Page: 91 / 98

7-3 (E)
DWT-B30
7-2. Pin Description of CPU (IC402 on the DPR-396 Board)
Pin No. Pin name User pin name I/O Description
1 PE6/INT6/AIN0 ZB_REQ_INT I REMOTE CPU INTERRUPT
2 PE7/INT7/AIN1/UVCON
3 UVCC
4 D
_
D
_
I/O USB DATA LINE
5 D
+
D
+
I/O USB DATA LINE
6 UGND UGND GND
7 UCAP UCAP VCC
8 VBUS VBUS I VBUS DETECT
9 PE3/IUID UID I USB OTG DETECT
10 PB0/SS/PCINT0 LNA_CONT O RF LNA CONTROL
11 PB1/PCINT1/SCLK SPI1_SCK O SPI1 CLOCK
12 PB2/PDI/PCINT2/MOSI SPI1_MOSI O SPI1 DATA OUT
13 PB3/PDO/PCINT3/MISO SPI1_MISO I SPI1 DATA IN
14 PB4/PCINT4/OC2A ZB_RESET O REMOTE CPU RESET
15 PB5/PCINT5/OC1A SET I SET BUTTON MONITOR
16 PB6/PCINT6/OC1B PLUS I PLUS BUTTON MONITOR
17 PB7/PCINT7/OC0A/OC1C MINUS I MINUS BUTTON MONITOR
18 PE4/INT4/TOSC1 PFI I POWER FAIL INTERRUPT
19 PE5/INT5/TOSC2 EEP_WP O EEPROM WRITE PROTECT CONTROL
20 RESET RESET I RESET
21 VCC1 VCC VCC
22 GND1 GND GND
23 XTAL2
24 XTAL1 XTAL1 I CRYSTAL OSCILLATOR
25 PD0/OC0B/SCL/INT0 SCL O I2C CLOCK
26 PD1/OC2B/SDA/INT1 SDA I/O I2C DATA
27 PD2/RXD1/INT2 SPI2_MISO I SPI2 DATA IN
28 PD3/TXD1/INT3 SPI2_MOSI O SPI2 DATA OUT
29 PD4/ICP1 FPGA_CS O FPGA SELECT
30 PD5/XCK1 SPI2_SCK O SPI2 CLOCK
31 PD6/T1 VBUS_CONT O VBUS POWER CONTROL
32 PD7/T0 PROG_B O FPGA CONFIGURATION RESET
33 PE0/WR
34 PE1/RD INIT_DONE I FPGA INITIALIZE STATUS
35 PC0/A8 POW_CONT O POWER SW CONTROL
36 PC1/A9 POW_SW I POWER SWITCH STATUS
37 PC2/A10 CS_G O DECORDER G PIN CHIP SELECT
38 PC3/A11/T3 CS_C O DECORDER C PIN CHIP SELECT
39 PC4/A12/OC3C D
+
2.8V_CONT O D
+
2.8V POWER CONTROL
40 PC5/A13/OC3B TX_POW_H/L O RF POWER SELECT
41 PC6/A14/OC3A PLL_LD I PLL LOCK DETECT
42 PC7/A15/IC3/CLK0 SLEEPS/P_G O S/P IC ENABLE
43 PE2/ALE/HWB FLASH_CS O FPGA FLASH ROM CHIP SELECT
44 PA7/AD7 CS_B O DECORDER C PIN CHIP SELECT
45 PA6/AD6 OEL_D/C O OLED DATA/COMMAND SELECT
46 PA5/AD5 OEL_RES O OLED RESET