Sony Cyber-shot PRO DSC-D700, Service Manual

Page: 99 / 116

4-11 DSC-D700 (UC,CE)
4-6. FUNCTION DESCRIPTION OF SY-264 BOARD
Functional outline of SY-264 board
.
The SY-264 board mounts a system control block with main microcomputer
IC001 in the center, a compression/expansion processing block consisting of
frame memory IC401 (on the FM-63 board) and JPEG coder IC003 that inputs
and outputs video data, and a card interface processing block.
Function description of main blocks
.
CPU block (IC001 and IC008)
The CPU block uses a 32-bit single-chip RISC microcomputer (SH-2) as main
microcomputer IC001 and controls the whole system. IC008 is a voltage detector
of 2.7 V. The detected output signal is combined with the SH reset signal from a
key/LCD control microcomputer (IC501 on the KC-47 board) by IC009 and input
to the reset pin (108) of IC001.
.
CPU peripheral block (IC011 to IC014, and IC002)
The CPU peripheral block consists of 4M-byte flash ROM (IC012), 16M-byte
DRAMs (IC013 and IC014), 64k-byte EEPROM (IC011), and a peripheral device
control circuit (IC002).
The peripheral device control circuit (IC002) consists of the following; a CPU
interface block (D0-D15, A1-A14, A21, interrupt INT (193), WAIT (194), and
control pulses), a JPEG control block (JA1-JA10, JCS (96), JRD (97), JWR (98),
JRQ (99), and JAK (100)), a key/LCD control microcomputer (IC501 on the KC-
47 board) interface block, a camera microcomputer (IC301 on the CA-33 board)
interface block, a card control block (CD0-CD15, CA0-CA10, CWE (11), COE
(10), CCE1 (8), and CCE2 (9)), and a battery check control block (TXBAT (145)
and RXBAT (144)).
.
JPEG block (IC003 and IC002)
During compression, the video data that is output from a frame memory controller
(IC401 on the FM-63 board) and read from DRAMs (IC404 and IC405 on the
FM-63 board) is input to the pins (PIXEL4 through PIXEL11) of JPEG coder
IC003. At that time, the video data is divided into the 8-by-8 (8 x 8)-pixel block
of Y, Cb, and Cr and input to IC003 in the order of YYCbCr.
The compressed data is input to DRAMs IC013 and IC014 by the DMA data
transfer between the JPEG coder (IC003) and DRAMs (IC013 and IC014).
During expansion, the compressed data output from DRAMs IC013 and IC014 is
input to JPEG coder IC003 by the DMA data transfer.
The control signals (EOS (34), DSYNC (37), and STOP (33)) required for the
JPEG coder are produced by a frame memory controller (IC401 on the FM-63
board).