K850
1203-2528 rev. 1
APPENDIX
Components D2010 - D2105 - D2404
A
P
P
E
NDIX
Logic diagram
AI13469
A-A0-A-Amax
A-DQ0-A-DQ15
A-V
DDQ
M39P0R09080E4
M39P0R01080E4
A-G
A-E
A-V
SS
16
A-W
A-RP
A-WP
A-V
DD
A-DPD
A-V
PP
A-L
A-K
A-WAIT
13
B-A0-B-A12
B-DQ0-B-DQ15
B-V
DD
B-CAS
B-VSS
16
B-RAS
B-V
DDQ
B-BA0-B-BA1
2
B-K
B-KE
B-W
B-UDQM
B-LDQM
B-E
Signal names
y
ll
a
n
r
e
t
n
I
d
e
t
c
e
n
n
o
C
t
o
N
C
N
d
e
t
c
e
n
n
o
C
y
ll
a
n
r
e
t
n
I
s
a
e
s
U
t
o
N
o
D
U
D
Flash memory signals
A-A0-A-Amax
(1)
Address Inputs
A-DQ0-A-DQ15
Data Inputs/Outputs
A-E
Chip Enable input
A-G
Output Enable Input
A-W
Write Enable input
A-RP
Reset input
A-WP
Write Protect input
A-L
Latch Enable input
k
c
o
l
C
t
s
r
u
B
K
-
A
A-WAIT
Wait Output
A-DPD
Deep Power-Down
A-V
DDQ
Power Supply for I/O Buffers
A-V
PP
Optional Supply Voltage for Fast Program & Erase
A-V
DD
Power Supply
A-V
SS
Ground
Low Power SDRAM signal
B-A0-B-A12
Address Inputs
B-DQ0-B-DQ15
Data Inputs/Outputs
B-E
Chip Enable Input
B-W
Write Enable input
t
u
p
n
i
k
c
o
l
C
M
A
R
D
S
P
L
K
-
B
t
u
p
n
i
e
l
b
a
n
E
k
c
o
l
C
M
A
R
D
S
P
L
E
K
-
B
B-CAS
Column Address Strobe Input
B-RAS
Row Address Strobe Input
B-BA0, B-BA1
Bank Select Inputs
B-UDQM
Upper Data Input/Output Mask
B-LDQM
Lower Data Input/Output Mask
B-V
DD
Power Supply
B-V
DDQ
Input/Output Supply voltage
B-V
SS
Ground
TFBGA connections (top view through package)
AI13470
NC
A-A25
A-VSS
B-VDD
A-WP
H
A-VDD
D
C
NC
NC
B
B-A9
A
8
7
6
5
4
3
2
1
A-A14
A-A22
G
F
E
A-A20
DU
B-KE
NC
A-A21
A-VSS
B-A7
B-E
B-K
B-A6
9
A-A15
A-VSS
M
L
K
J
NC
A-A6
NC
NC
A-A4
A-A19
B-RAS
NC
NC
NC
B-VDD
B-A3
B-BA1
NC
A-VSS
A-VSS
B-A10
A-DPD
B-A1
A-VSS
B-VDDQ
NC
NC
B-CAS
B-W
A-E
NC
A-W
B-LDQM
B-VDDQ
B-UDQM
B-VDDQ
B-VDD
DU
B-A2
B-BA0
B-A0
B-A11
B-A12
B-A8
A-A13
A-A12
A-A10
A-A11
A-A8
A-A9
NC
A-A5
A-A3
A-A18
A-A16
NC
NC
NC
A-
WAIT
A-VSS
A-A24
NC
A-A7
A-A17
A-A23
NC
A-VSS
NC
NC
A-VDD
NC
NC
A-VPP
A-RP
11
10
12
B-A4
DU
DQ4
NC
A-DQ5
A-DQ12
A-L
NC
A-DQ7
NC
NC
A-VDDQ
A-K
DU
A-DQ6
A-DQ14
A-DQ10
A-G
A-DQ9
B-A5
A-VSS
A-VDDQ
A-VSS
A-DQ1
A-VDDQ
A-DQ11
A-VSS
A-DQ15
NC
A-
DQ13
A-VSS
A-DQ3
A-VDDQ
NC
A-DQ2
R
P
N
A-A0
B-VSS
B-DQ0
DU
B-DQ13
NC
B-DQ2
B-DQ4
B-DQ6
B-DQ9
B-DQ11
B-VSS
B-VSS
DU
A-A1
A-A2
A-VSS
NC
B-VSS
B-DQ1
B-DQ3
B-DQ5
B-DQ7
B-DQ8
B-DQ10
B-DQ12
B-DQ15
DU
NC
A-DQ8
A-DQ0
B-DQ14
NC
DU
NC
B-VDDQ
NC
D
E
b
A
B
C
D
E
F
G
H
J
K
8
7
6
5
4
3
2
1
1
1
10
9
L
M
N
P
R
Top View - Ball
Side Down
S1
S2
e
A
Y
A2 A1
12
Ball one Corner
(BOTTOM VIEW)
OE
GND
V
CC
Y
A
1
4
2
3
5
FUNCTION TABLE
INPUTS
OUTPUT
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
logic diagram (positive logic)
Y
A
OE
1
4
2
Block diagram
REGISTER
MAP
ULPI
INTERFACE
CONTROLLER
USB DATA
SERIALIZER
USB DATA
DESERIALIZER
HI-SPEED
USB ATX
DM
DP
STP
DIR
NXT
DATA
[7:0]
8
004aaa862
CLOCK
TERMINATION
RESISTORS
PLL
CRYSTAL
OSCILLATOR
VOLTAGE
REGULATOR
BAND GAP
REFERENCE
VOLTAGE
RREF
internal power
VCC
REG1V8
REG3V3
GLOBAL
CLOCKS
XTAL2
XTAL1
V
CC(I/O)
interface voltage
V
BUS
ISP1508
ULPI
INTERFACE
V
REF
CHIP_
SEL
UART
BUFFER
DATA[1:0]
DDR OR SDR
SELECTION
CLOCK
FREQUENCY
SELECTION
ID
DETECTOR
SRP CHARGE
AND DISCHARGE
RESISTORS
OTG MODULE
V
BUS
COMPARATORS
PORT
POWER
CONTROL
FAULT
PSW_N
CFG0
CFG1
CFG2
POWER-ON
RESET
POR
GND
ID
C2
C1
D1
E2
D3
F4
F3
D4
E3
F5
F6
C3
E1
B4
B3
E6
E5
D6
D5
C6, B6, A6,
A5, A3, A2,
A1, B1
B2, B5
A4
E4, C5, D2
Pin con
fi
guration
004aaa863
ISP1508
Transparent top view
F
E
D
C
A
B
2
4
6
1
3
5
ball A1
index area
K850
A
P
P
E
NDIX
D2010 Memory MCP 1 Gbit+0 kbit 0, Hz 0, V 1200-1356
D2105 IC Single Bus Buffer Gate 1200-0425
D2404 IC IF ISP 1508 ES3 1200-1694
SEMC Troubleshooting Manual
76
(101)
SEMC Electrical Repair Manual
