K850
1203-2528 rev. 1
FUNCTIONAL OVERVIEW
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The front-end zero IF I and Q outputs are applied to the integrated low-pass channel filter. The
filter is self-calibrated with a cut-off frequency around 2.15 MHz. The filter may be configured in
the normal mode as an all-pole configuration or in the hybrid mode as a pole/stopband zero
configuration. The hybrid mode is used in Bands II and V for suppression of narrowband
blocking signals. Gain in the N300 may be programmed over the serial bus, with up to
approximately 85 dB typical range. A zero IF output buffer provides close rail-to-rail outputs
signal.
Bluetooth and FM Radio
The STLC2592 circuit N1400 combines Bluetooth and FM tuner functionality into one unit.
Bluetooth
The Bluetooth implementation is compliant with Bluetooth specification 2.1 + EDR.
The Bluetooth
TM
transceiver has frequency channels with 1 MHz separation from 2402 to 2480
MHz. The same band is used for both transmission and reception. This gives 79 frequency
channels.
Receiver
The first stage of the receiver is an external antenna filter, which suppresses unwanted
frequencies. The receiver is of a “near-zero” IF receiver architecture. The local oscillator is
generated by a frequency synthesizer, which allows the receiver to be set at frequencies in
intervals of 1 MHz. The synthesizer is controlled from the logic part. The received signal is
sampled in the logic for later signal processing.
Transmitter
The synthesizer generates the TX frequency which modulated by the BT baseband block. It is
then amplified. The BT system is a class 1 device with maximum of +4 dBm output power
(minimum setting is about -50 dBm).
FM Radio
FM Receiver
The receiver uses a digital low-IF architecture. The receive (RX) section integrates a low noise
amplifier (LNA) supporting the worldwide FM broadcast band (76 to 108 MHz). An automatic
gain control (AGC) circuit controls the gain of the LNA to optimize sensitivity and rejection of
strong interferers. An image-reject mixer down converts the RF signal to low-IF. The
quadrature mixer output is amplified, filtered and digitized with high resolution analog-to-digital
converters (ADCs). This advanced architecture allows the use of digital signal processing (DSP)
to perform channel selection, FM demodulation and stereo audio processing.
Tuning
The receiver uses frequency synthesizer technology including a completely integrated VCO. The
frequency synthesizer generates the quadrature local oscillator signal used to convert the RF
input down to a low intermediate frequency. The VCO frequency is locked to the reference clock
and adjusted with an automatic frequency control (AFC) servo loop during reception. The tuning
frequency is defined as:
Freq (MHz) = Spacing (kHz) × C Bottom of Band (MHz)
E t
l C
t
External units are connected to the transceiver by means of a 12-pin connector on the bottom
of the phone. The pin numbering is starting from the right when looking at the system
connector with the front up.
System connector pin out:
1
Vbus
2
SP
Ref
5
Sp
L
/
DBG
TX
6
Sp
R
/
DBG
RX
4
Mic-
/
Aux in
R
7
Video
/
Strobe
8
AID
/
ACB
/
Vpp
Flash
9
GND
10
D+
/
DTMS
3
Mic+
/
Aux in
L
11
D-
/
DFMS
12
DCIO
Clocks
Clock Distribution
The clocking for the access and application subsystems is separated. This means that they can
wake up or go to sleep mode independently. The access subsystem is clocked by the 26 MHz
Voltage Controlled Crystal Oscillator (VCXO) located in the GSM/EDGE module N1200 (Thor).
When the access subsystem has a job to do, the Master Clock (MCLK) signal is requested from
the RF part. Most other clocks needed within the access subsystem are generated from the
MCLK. Some minor parts like sleep timer and cable detect use the 32 kHz real-time clock. The
32 kHz real-time clock clocks the application subsystem, and all other internal clocks needed
within the application subsystem are generated from this clock. However, when audio is
transferred between the application and the access subsystems, the MCLK is used.
Master Clock
(26 MHz)
The 26.00 MHz VCXO-based MCLK is distributed as a square wave signal from the GSM/EDGE
circuit. In order to have full control over the load on the MCLK, only the access side of the
digital baseband controller is allowed to request the MCLK. However, by indirect means also the
application side CPU can issue the request. A VCXO-based square wave is also distributed to the
WCDMA circuit, but is turned on only upon a command from the digital baseband controller.
Real-time Clock
(32. 768 KHz)
A 32.768 kHz crystal oscillator provides a low frequency clock whenever the phone has power.
This clock is used to keep the Real-Time Clock (RTC) block operational, so that the phone can
keep track of the time and date. The low frequency clock is generated in the analog baseband
controller N2000 (Vera) and distributed to the digital baseband controller D2000 (Anja), and if
necessary to external devices like Bluetooth, FM radio and A-GPS.
Technical Description
SEMC Troubleshooting Manual
70
(101)
