SMART Embedded Computing MVME2502, Installation And User Manual

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138 MVME2502 Installation and Use (6806800R96L)
Programming Model
Programming Model
7.7.1 System Clock
The system and DDR clock is driven by ICS840S07I device. The following table defines the
clock frequency.
7.7.2 Real Time Clock Input
The RTC clock input is driven by 1 MHz clock generated by the CPLD. This provides a fixed
clock reference for the QorIQ P2020 PIC timers which the software can use as a known
time reference.
TSI384 CLK_PCIEC3 100MHz ICS9FG111 DIFF
88SE9125
CLK_88SE9125_PCIE_100
MHZ
100MHz ICS9FG112 DIFF
CPLD CLK_CPLD 1.8432MHz Oscillator +3.3V
USB CLK_USB_1_24MHZ 24MHz Oscillator +3.3V
QorIQ P2020 CPU_RTC 1MHz CPLD +3.3V
PMC CLK_PMC1
33/66/100/133
MHz
TSI384 +3.3V
TSI148 CLK_PCI_BR3 133MHz ICS840S07I +3.3V
RTC CLK_32K 32.768KHz DS32KHz +3.3V
CPLD CPU_LCK0 25MHz QorIQ P2020 +3.3V
QUART CLK_QUART 1.8432MHz CPLD +3.3V
ICS83905 CLK_25MHZ_ICS9FG108 25MHz ICS83905AGILF +3.3V
Table 7-6 Clock Distribution (continued)
Device Clock Signal Frequency
Clock Tree
Source
VIO
Table 7-7 System Clock
SYSCLK CORE CCB Clock (Platform) DDR3 LBC
100MHz 800/1200MHz 400MHz 400MHz 25MHz