SMART Embedded Computing MVME2502, Installation And User Manual

Page: 137 / 150

Programming Model
MVME2502 Installation and Use (6806800R96L) 137
7.7 Clock Distribution
The clock function generates and distributes all the clocks required for system operation.
The ICS9FG108 is used to generate all the required PCI-E clocks. The 25MHz clocks for
the Ethernet PHY and SATA bridge are supplied by ICS83905 device. Most of the QorIQ
P2020 clocks are generated by ICS840S07I device. Additional clocks required by individual
devices are generated near the devices using individual oscillators. The following table lists
the clocks required on the MVME2502 along with the frequency and source.
EHTR Extended hold time on read accesses.
0 - The memory controller generates normal timing. No additional cycles are
inserted
EAD External address latch delay
0 - No additional bus clock cycles (LALE asserted for one bus clock cycle
only)
Table 7-6 Clock Distribution
Device Clock Signal Frequency
Clock Tree
Source
VIO
QorIQ P2020 CPU_SYSCLK 100MHz ICS840S07I +3.3V
QorIQ P2020 CPU_DDR_CLK 100MHz ICS840S07I +3.3V
QorIQ P2020 CLK_PCI_BR3 133MHz ICS840S07I +3.3V
QorIQ P2020 EC_GTX_CLK125 125MHz ICS840S07I +3.3V
ICS840S07I CLK_25MHZ_ICS840S07 25MHz ICS83905AGILF +3.3V
88SE9125 CLK_88SE9125_25MHZ 25MHz ICS83905AGILF +3.3V
ICS9FG108 CLK_25MHZ_ICS9FG108 25MHz ICS83905AGILF +3.3V
BCM54616S BP_PHY_25MHZ_CLK 25MHz ICS83905AGILF +3.3V
BCM54616S FP_PHY_25MHZ_CLK 25MHz ICS83905AGILF +3.3V
BCM54616S SW_25MHZ_CLK 25MHz ICS83905AGILF +3.3V
XMC CLK_XMC1 100MHz ICS9FG108 DIFF
QorIQ P2020 SD_REF_CLK 100MHz ICS9FG109 DIFF
TSI384 CLK_PCIEC1 100MHz ICS9FG110 DIFF