
SLE2000 HFO Service Manual
Doc No. SM/0001: Issue 7.0
Page 11 of 84
modes of HFO operation are selected. In all other modes the alarm is disabled by grounding the output
(U27/5). The output signal is taken to one of the inputs on the Alarm Board (A0738/02).
3.1.4.4 Dual Fan Fail Alarm
This circuit operates audible and visual alarms if the speed of either fan motor falls below approx. 75% of
normal rate. Current pulses from the motor commutation develop pulses which are compared with a
reference voltage in U23A and B. This results in output pulses from U23/1 and U23/7 for each fan. The
negative going edges trigger U22 which remains re-triggered(logic 1) as long as the interval between
triggered pulses is greater than 5ms. The data output of U22 is fed to U24 and is latched in the latter by
the positive going edge of the pulse from U22. The output of U24 remains at logic 0 as long as the interval
between pulses from the motor is less than 5ms. However, if the motor runs slowly or stops or is open
circuit then the output of U24 goes to logic 1 and enables the fan fail alarm via D2 or D3. MOS1 and
MOS4 hold the reset pins of U24 inactive as long as there are motor pulses. U24 is reset during power up
or if motor pulses fail and enables the fan fail alarm.
3.1.4.5 LED Bargraph
This circuit simultaneously displays, on a 40 segment bargraph module, low, fail to cycle, and high alarm
pressure thresholds as well as the instantaneous pressure signal (derived from the A0702/02 buffered
transducer output). These four input voltages are first buffered and conditioned before being time
multiplexed via the 4066 analogue switch (U31). Oscillator U19 drives a counter (U18) which is used to
sequentially enable U31A,B,C and D. The multiplexed signal is then used to drive the bargraph PCB
(A0737).
3.1.4.6 Processor System
All alarm parameters are determined by potentiometer voltages representing fail to cycle, low and high
pressure thresholds. Also Timebase and pressure range switch settings, and CPAP mode status, patient
circuit pressure, HFO motor speed are all represented by voltages which enter the processor system via
addressable ADC0809 (U5)
U7 and its peripheral passive components form a one second interrrupt generator which is used by the
processor system to determine a 1 minute period for the screen freeze function.
The watchdog device U12 will provide a reset pulse for the processor (U10) on power up, power down
and brownout conditions. It will also monitor U13/13, (VIA- Versatile Interrupt Adaptor) and if no
change of state is recognised on this line (indicating a processor fail) within 1.6 seconds then the wathdog
will provide a reset pulse for the processor. Whilst no pulse is recognised on U13/13 the watchdog will
also provide a signal out on U12/14 indicating HFO CPU (A0736/01) system fail which is sent to the
Alarm PCB.
3.1.5 B
ARGRAPH
D
ISPLAY
B
OARD
A
SSEMBLY
(A0737)
Summary of Contents for SLE2000 HFO
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Page 29: ...SLE2000 HFO Service Manual Doc No SM 0001 Issue 7 0 Page 29 of 84 5 2 A0701 02 ...
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Page 52: ...SLE2000 HFO Service Manual Doc No SM 0001 Issue 7 0 Page 52 of 84 5 9 SERIAL INTERFACE OPTION ...
Page 54: ...SLE2000 HFO Service Manual Doc No SM 0001 Issue 7 0 Page 54 of 84 5 10 WIRELOOM ...
Page 55: ...SLE2000 HFO Service Manual Doc No SM 0001 Issue 7 0 Page 55 of 84 5 11 FRONT PANEL ...
Page 58: ...SLE2000 HFO Service Manual Doc No SM 0001 Issue 7 0 Page 58 of 84 5 14 ELECTRONIC CHASSIS ...
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