6.2 Programming the Clock Path
Given a valid VCO frequency for the M unique frequencies, segregate the N-M equal frequencies into outputs from each group Gx in
Table 6.2 Output Frequency Variables Grouping and Mapping to Actual Output Pins on page 18
. When arranging outputs, care must be
taken to minimize crosstalk (without violating the constraints imposed from the grouping of output frequencies into the VDDO “banks”).
Whenever several high frequencies, fast rise time, large amplitude signals are all close to one another, the laws of physics dictate that
there will be some amount of crosstalk. The jitter of the Si5332 is low, and, therefore, crosstalk can become a significant portion of
the final measured output jitter. Some of the source of the crosstalk will be the Si5332 and some will be introduced by the PCB. For
extra fine tuning and optimization in addition to following the usual PCB layout guidelines, crosstalk can be minimized by modifying the
arrangements of different output clocks:
1. Avoid adjacent frequency values that are close. A 155.52 MHz clock should not be next to a 156.25 MHz clock. If the jitter
integration bandwidth goes up to 20 MHz, then keep adjacent frequencies at least 20 MHz apart.
2. Adjacent frequency values that are integer multiples of one another are okay and these outputs should be grouped accordingly.
3. Unused outputs can be used to separate clock outputs that might otherwise interfere with one another. If some outputs have tight
jitter requirements while others are relatively loose, rearrange the clock outputs so that the critical outputs are the least susceptible
to crosstalk. These guidelines typically only need to be followed by those applications that wish to achieve the highest possible
levels of jitter performance. Because CMOS outputs have large pk-pk swings and do not present a balanced load to the VDDO
supplies, CMOS outputs generate much more crosstalk than differential outputs. For this reason, CMOS outputs should be avoided
whenever possible. When CMOS is unavoidable, even greater care must be taken with respect to the above guidelines.
An output multiplexer (output mux) or crosspoint mux needs to be programmed such that each group Gx is set to the correct O-divider,
N-divider, or input clock (in the case of buffering). Each output, Foutxy, has this common divider or input clock reference that needs to
be set. The multiplexer setting that routes the correct divider/clock source to the correct group is shown in the following table.
Table 6.5. Output Mux (Crosspoint Mux) Settings
Register Field
Description
omuxx_sel0
Selects output mux clock for output clocks in group Gx:
0 = PLL reference clock before pre-scaler
1 = PLL reference clock after pre-scaler
2 = Clock from input buffer 0
3 = Clock from input buffer 1
omuxx_sel1
Selects output mux clock for output clocks in group Gx:
0 = HSDIV0
1 = HSDIV1
2 = HSDIV2
3 = HSDIV3
4 = HSDIV4
5 = ID0
6 = ID1
7 = Clock from omux1_sel0
The final steps will be to program the
hsdiv
and
id (N)
dividers. The equations below show the relationship between
hsdiv
,
id
divider
values with their associated output frequency. They also show the register fields that need to be programmed to set up the divider
values correctly. The register field and the divider value are both denoted by:
hsdivxa
_
div
=
vcoFreq
Foutxa × Rxa
The
id
(i.e. N) dividers are calculated as below:
idxa
=
vcoFreq
Foutxa × Rxa
Si5332-AM1/2/3 Automotive Grade Device Reference Manual • Programming the Volatile Memory (Registers)
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