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6.1 Programming the PLL

The PLL programming involves three distinct constraints:

1. The minimum and the maximum frequencies possible for the PFD (Phase Frequency Detector) at lock. This is set by the reference

frequency that sets the input divider P and the active input clock as selected by the IN SEL pins or registers.

2. The VCO frequency that is set by feedback divider (Mn/Md) and the PFD frequency also has a limited range that is unique to

Si5332.

3. The PLL closed loop transfer function characterized by its loop band width and peaking is set by programming the loop parame-

ters.

The table below lists the constraints for the PLL reference frequency and the VCO frequency. The PLL reference frequency
(

pllRefFreq

) and the VCO frequency (

vcoFreq

) are related by the equation below:

vcoFreq

pllRefFreq

× (

Mn
Md

)

For a given plan, the

pllRefFreq

can be readily solved as it is derived from the input clock frequency. To get to this optimization, the

“active” input to the PLL must be selected from the XA/XB, CLKIN_1, CLKIN_2, in 1 p/m input clocks using either the IMUX_SEL regis-
ter field or the CLKIN_SEL pins (if CKIN_SEL pins are available in the custom part that was chosen to reprogrammed).

PllRefFreq

given by the In-Freq (active clock input frequency) and P as:

PllRefFreq

InFreq

Table 6.1. Constraints for PLL Reference Frequency and VCO Frequency

Field Name

Value

Description

pllMinRefFreq

10 MHz

The minimum reference frequency the PLL can tolerate

pllMaxRefFreq

50 MHz

The maximum reference frequency the PLL can tolerate

vcoCenterFreq

2.5 GHz

The center frequency of the VCO’s tuning range

vcoMinFreq

2.375 GHz

The minimum frequency of the VCO’s tuning range

vcoMaxFreq

2.675 GHz

The maximum frequency of the VCO’s tuning range

List all required output frequencies, Fxy, in groups denoted by Gx, where x = 0,1,2,3,4,5 and y = a,b,c. This grouping is done such that
frequencies related to each other by rational fractions of integers between 1 and 63 are in that group. For example, 100 MHz/80 MHz
= 5/4 is a rational fraction. Each group Gx is associated with a single output voltage supply driver inside Si5332 and is shown in

Table

6.2 Output Frequency Variables Grouping and Mapping to Actual Output Pins on page 18

. The table also shows the output frequency

symbol Fxy mapped to the output name in the Si5332 pin descriptions. The integer O-dividers are denoted by hsdiv. Each Oi divider
maps to a hsdivi in the solver where i is an integer between 0 and 4. Similarly, the two Multisynth N-dividers, Nj map to IDj and j = 0 or
1. The constraints for these divider values are listed in

Table 6.3 Constraints for hsdiv and id on page 19

Table 6.2. Output Frequency Variables Grouping and Mapping to Actual Output Pins

Si5332 12-Output Part

Output Pair

(Future Device)

Si5332 8-Output Part

Output Pair

Si5332 6-Output Part

Output Pair

Output Frequency

Variable for Solver

The Output Frequency