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8317
8317
N/B Maintenance
N/B Maintenance
5.3 ULI M1573 South Bridge(1)
PCI Interface
Pin Name
I/O Type Description
PCICLK I
PCI Clock for Internal PCI Interface.
This is a PCI clock input that is controlled by clock generator.
PCI_OUTCLK[9:0] O
PCI Clock Output.
This is PCI output clocks for PCI device.
PCICLK_FBKO O
PCI Clock Feedback Out Signal.
This is a PCI clock feedback
input path.
PCICLK_FBKI I
PCI Clock Feedback In Signal.
This is a PCI clock feedback
input path.
PCIREQ#[3:0]
PCIREQ#[6:4]/
RUNGPI[6:4]
I
PCI Requests.
PCI master requests for the PCI bus ownership. M1573 supports
up to 7 masters on the PCI bus. PCIREQ#[0] is programmable
to have the highest priority of the PCI arbitration for supporting
PCI-based 1394 controller.
PCIREQ#[6:4] can be configured as RUNGPI.
PCIGNT#[3:0]
PCIGNT#[6:4]/
RUNGPO[6:4]
O
PCI Grants.
PCI master be granted for the PCI bus ownership. M1573
supports up to 7 masters on the PCI bus. PCIGNT#[6:4] can be
configured as RUNGPO.
PIRQ#[D:A]
PIRQ#[H:E]/
RUNGPI[10:7]
I
PCI Interrupt Requests.
In legacy 8259 mode, PIRQ#[H:A] signals can be routed to
legacy IRQs through the routing table defined in the PCI-legacy
device configuration registers 4Bh – 48h.
In APIC mode, PIRQ#[A] is connected to entry-16, PIRQ#[B]
to entry-17, PIRQ#[C] to entry-18, PIRQ#[D] to entry-19,
PIRQ#[E] is connected to entry-20, PIRQ#[F] to entry-21,
PIRQ#[G] to entry-22, and PIRQ#[H] to entry-23.
PIRQ#[H:E] can be configured as RUNGPI.
CLKRUN#/
RUNGPO[9]
I/O
O
PCI Clock Run control.
This signal is used to support PCI Clock Run CLKRUN#
protocol. It can also be configured as RUNGPO.
AD[31:0] I/O
PCI Address and Data Multiplexed Bus.
During the first clock of a PCI transaction, AD[31:0] contain a
physical address. During subsequent clocks, AD[31:0] contain
data.
CBE#[3:0] I/O
PCI Bus Command and Byte Enable.
During address phase, CBE#[3:0] define the Bus Command.
During the data phase, CBE#[3:0] define the Byte Enables.
PCI Interface (Continued)
Pin Name
I/O Type Description
FRAME# I/O
PCI Cycle Frame.
Cycle Frame is driven by current initiator to indicate the
beginning and duration of a PCI access.
IRDY# I/O
PCI Initiator Ready.
Initiator Ready indicates the initiator’s ability to complete the
current data phase of the transaction.
TRDY# I/O
Target Ready.
Target Ready indicates the target’s ability to complete the
current data phase of the transaction.
DEVSEL# I/O
PCI Device Select.
This signal indicates that the target device has decoded the
address as its own cycle.
STOP# I/O
Cycle Stop Request.
Cycle Stop indicates the target is requesting the master to stop
the current transaction.
SERR# I
PCI System Error.
This signal may be pulsed active by any agent that detects a
system error condition. When SERR# is sampled low, the
M1573 will assert NMI to generate non-maskable interrupt to
CPU.
PAR I/O
PCI Parity Signal.
PAR is an Even Parity and is calculated on AD[31:0] and
CBE#[3:0].
PCIRST# O
PCI Bus Reset.
This is an output signal to reset the entire PCI Bus.
PME# I/O
PCI Power Management Event.
This signal is used by a PCI device to request a change of its
power consumption state. Typically, an active PME# issued by
a device is to wake up a power saving state of device or system
to the fully operational state.
