Sinty Zhang 8317, Service Manual

Page: 90 / 148

89
8317
8317
N/B Maintenance
N/B Maintenance
5.2 ATI RS480M North Bridge(4)
LVDS Interface (Continued)
Pin Name Type Power
Domain
Ground
Domain Integrated
Termination
Functional Description
TXCLK_
LN O LVDDR1
8A
LVSSR None LVDS lower clock channel (-)
Transmitting at pixel clock rate, up to
85MHz pixel clock. This channel is used
as the transmitting channel
in single channel LVDS mode.
LPVSS Gnd – – – LVDS PLL macro ground pin.
LVDDR1
8D Pwr – – – 1.8V LVDS Digital Power, used for the
digital portions of the LVDS transmitter.
LVSSR Gnd – – – LVDS IO ground pin.
LVDS_BL
ON I/O VDDR3 VSS 50k Ω
programmable:
PU/PD/none
Digital panel backlight brightness control.
Active high. It controls
backlight on/off or acts as PWM output to
adjust brightness. If
LVDS_GEN_CNTL.LVDS_BL_MOD_E
N = 0, the pin controls backlight on/off.
Otherwise, it is the PWM output to adjust
the brightness.
LVDS_GEN_CNTL.LVDS_BL_MOD_L
EVEL can be used to control the backlight
level (256 steps) by means of pulse width
modulation. The duty cycle of the
backlight signal can be set through the
LVDS_GEN_CNTL.LVDS_BL_MOD_L
EVEL bits. For example, setting these bits
to a value of 32 will set the on-time to
32/256*(1/f) and the off-time to
(256-32)/256*(1/f), where f is the
XTALIN frequency and is typically
14MHz. Note that the PWM frequency can
range from 5Hz to 50KHz and
is set by
LVDS_PWM_CNTL.PWM_CLK_CONF.
For more information, refer to the Register
Reference Manua
l.
In CPIS mode, LVDS_BLON is
VARY_BL as defined in CPIS.
PWM mode should be enabled.
LVDS_BLEN should be connected to
ENA_BL, which turns the backlight AC
inverter on/off.
LVDS Interface (Continued)
TXCLK_
LP O LVDDR1
8A
LVSSR None LVDS lower clock channel (+)
Transmitting at pixel clock rate, up to
85MHz pixel clock. This channel is used
as the transmitting channel
in single channel LVDS mode.
LPVDD Pwr – – – Power for LVDS PLL macro (1.8V).
LVDDR1
8A A-Pwr – – – 1.8V LVDS Analog Power, used for the
output stage of the transmitter. This power
supply needs to be adequately filtered to
prevent noise injection.
Pin Name Type Power
Domain
Ground
Domain Integrated
Termination
Functional Description
LVDS_DI
GON I/O VDDR3 VSS 50k Ω
programmable:
PU/PD/none
Control Panel Digital Power On/Off.
Active high.
LVDS_BL
EN I/O VDDR3 VSS 50k Ω
programmable:
PU/PD/none
Enables Backlight for CPIS compliant
LVDS panels. Active high.Controlled by
the hardware power up/down sequencer.
For more details, refer to
Figure 4-3,
“LCD Panel Power Up/Down Timing,” on
page 4-
3.
1 x 16 Lane PCI Express Interface for External Graphics
Pin Name Type Power
Domain
Ground
Domain Integrated
Termination
Functional Description
GFX_TX[
15:0]P,
GFX_TX[
15:0]N O VDDA_1
8
VSSA 50 Ω between
complements
Transmit Data Differential Pairs. Connect
to external connector for an
external graphics card on the motherboard
(if implemented).
GFX_RX[
15:0]P,
GFX_RX[
15:0]N I VDDA_1
8
VSSA 50 Ω between
complements
Receive Data Differential Pairs. Connect
to external connector for an
external graphics card on the motherboard
(if implemented).
GFX_CL
KP,
GFX_CL
KN I/O VDDA_1
8
VSSA 50 Ω between
complements
Clock Differential Pairs. Connect to
external clock generator when an
external graphics card is implemented.