91
8317
8317
N/B Maintenance
N/B Maintenance
5.2 ATI RS480M North Bridge(6)
Miscellaneous Pins
Pin Name Type
Power
Domain
Ground
Domain
Integrated
Termination
Functional Description
BMREQ#
Out
VDDR3
VSS
–
This pin is connected to the south bridge.
This signal indicates that there is a DMA
request from a PCI Express Bus device.
I2C_CLK
I/O
VDDR3
VSS
–
I2C interface clock signal. Can also be
used simultaneously as DDC interface
clock for the LVDS interface or the
external DVO interface. It can also be used
as GPIO.
I2C_DAT
A
I/O
VDDR3
VSS
–
I2C interface data signal. Can also be used
as GPIO.
DDC_DA
TA
I/O
VDDR3
VSS 50k
Ω
programmable:
PU/PD/none
Pin for additional DDC Data Channel for
the LVDS interface or the external DVO
interface. It makes use of I2C_CLK to
create an I2C interface. Can also be used
as GPIO.
STRP_DA
TA
I/O
VDDR3
VSS
–
I2C interface data signal for external
EEPROM based strap loading. See the
RS480M Strap Document for details on
the operation. Can also be used as GPIO or
NB Voltage throttling on mobile
platforms.
TESTMO
DE
I
VDDR3
VSS
–
When High, puts the RS480M in Tester
mode and disables the RS480M from
operating normally.
THERMA
LDIODE_
P,
THERMA
LDIODE_
N
A-O
–
–
–
Diode connections to external SM Bus
microcontroller for monitoring IC thermal
characteristics.
TMDS_H
PD
I
VDDR3
VSS
PU
TMDS Hot Plug Detect. “Hot Plug” panel
detection input pin that monitors if the
voltage is greater than 2.0V on the
hot-plugging line.
DFT_GPI
O[5:0]
I/O
VDDR3
VSS
PU
GPIO for DFT use.
Note:
Because DFT_GPIO[5, 1:0] are
used as strap pins (see
Table 3-15,
“Strap Definitions for the RS480M”
),
they cannot be used for general GPIO
functions.
Strap Definitions for the RS480M
Strap Function
Strap Pin
Description
LOAD_MEM_STRAPS
#
DFT_GPIO5* Selects loading of straps from MEM_DQ pins for debug
bus
0 : Capture MEM_DQ pins for debug bus straps.
1 : Use Default Values (Default)
Note : More information about straps on the MEM_DQ
pins is available in the Debug Bus specification.
HT_FREQ_OVERRIDE DFT_GPIO[4:3
]
Overrides HT Link frequency at power up
00 : Reserved – for testing only.
01 : Reserved – for testing only.
10 : Reserved – for testing only.
11 : 200 MHz (Default)
HT_WIDTH_OVERRI
DE
DFT_GPIO2 Override HT Link width at power up
0 : Reserved – for testing only.
1 : 8 Bit Link (Default)
LOAD_ROM_STRAPS
#
DFT_GPIO1* Selects loading of strap values from EEPROM
0: I2C master can load strap values from EEPROM if
connected, or use default values if not connected
1: Use Default Values (Default)
SIDE_PORT_EN#
DFT_GPIO0* Indicates if memory side port is available or not
0: Memory side port available
1: Memory side port NOT available (Default)
Not
e: Strap pins marked by “*” cannot be used for general GPIO functions.
PCI Express Interface for Miscellaneous PCI Express Signals
Pin Name Type
Power
Domain
Ground
Domain
Functional Description
PCE_ISE
T
Other VDDA_1
8
VSSA
Current Calibration for for Rx Channel
PCE_TXI
SET
Other VDDA_1
8
VSSA
Current Calibration for for Tx Channel
PCE_NC
AL
Other VDDA_1
8
VSSA
N channel Driver Compensation Calibration for Rx and Tx
Channels
PCE_PCA
L
Other VDDA_1
8
VSSA
P channel Driver Compensation Calibration for Rx and Tx
Channels
