CP2130-EK
Rev. 0.2
27
10.17. SPI Monitor Chip-Select Input Header (JP19)
The SPI_MON_CS signal can be configured to use one of the following three chip-select signals:
CS0 (Short Pins 1–2 on JP19)
CS1 (Short Pins 3–4 on JP19)
CS2 (Short Pins 5–6 on JP19)
See Table 15 for the SPI monitor chip-select input header pin definitions.
10.18. ADC SPI Header (JP21)
This header provides access to the ADC SPI signals (SDI, SCLK, SDO). Install shorting blocks to connect each
SPI signal to the appropriate CP2130 SPI pin. Table 16 lists the ADC SPI signals corresponding to each header
position.
10.19. VIO Header (JP22)
This header provides access to the CP2130 VIO pin. Install a shorting block on JP22 short VIO to VDD. See
Table 17 for the VIO header pin definitions.
Table 15. SPI Monitor Chip-Select Input Header Pin Definitions
SPI_MON_CS
Pins
CS0
JP19[1:2]
CS1
JP19[3:4]
CS2
JP19[5:6]
Table 16. ADC SPI Header Locations
ADC SPI Signal
CP2130
SPI Signal
Pins
SDI
MOSI
JP21[1:2]
SCLK
SCK
JP21[3:4]
SDO (Buffered)
MISO
JP21[5:6]
Table 17. VIO Header Pin Definitions
Pin #
Definitions
1
VDD
2
VIO
