CP2130-EK
Rev. 0.2
23
10.5. Power and SPI Test Points (J6)
Pins 1–6 of the test point header (J6) provide easy access to the GND, VDD, VIO, VDDSW, VREGIN, and VBUS
power signals. Pins 7–10 provide easy access to the SCK, MOSI, MISO, and GND SPI signals. See Table 3 for the
test point pin definitions.
10.6. VREGIN Input Header (JP1)
The CP2130 can be configured to operate in one of two power modes:
USB self-powered mode (Short Pins 1–2 on JP1)—VREGIN is shorted to VDD, the CP2130 internal
voltage regulator is disabled, and an external supply voltage must be connected to the VDD test point. Do
not exceed the maximum VDD voltage specification!
USB bus-powered mode (Short Pins 2–3 on JP1)—VREGIN is shorted to VBUS and the CP2130 internal
voltage regulator is enabled. The board VDD is powered by the CP2130 internal voltage regulator output.
See Table 4 for the VREGIN input header pin definitions.
Table 3. Power and SPI Pin Definitions
Type
Pin #
Definition
Power
1
GND
2
VDD
3
VIO
4
VDDSW (Switched Supply)
5
VREGIN
6
VBUS
SPI
7
SCK
8
MOSI
9
MISO
10
GND
Table 4. VREGIN Input Header Pin Definitions
Pin #
Definitions
1
VDD (Self-Powered)
2
VREGIN
3
VBUS (Bus-Powered)
