Silicon Laboratories CP2130 User Manual Download Page 21 | Manualshive

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CP2130-EK

Rev. 0.2

21

10.1. CP2130 Evaluation Board Components

Numerous input/output (I/O) connections are provided to facilitate prototyping using the evaluation board. Refer to
Figure 19 for the locations of the various I/O connectors. For each header in Figure 19, Pin 1 is indicated with a
square pin. Refer to Figure 20 for a complete schematic.

D1–D9

Green GPIO.0–GPIO.8 LEDs

D10

Green GPIO0.9 (SUSPEND) LED

D11

Red GPIO.10 (SUSPEND) LED

J3

CP2400 AB LCD header

J4

SPI monitor header

J5

Mini-USB connector

J6

Power and SPI test points

JP1

VREGIN input header

JP3–JP5

LED headers

JP6

SPI loopback header

JP9

ADC VDD header

JP10

ADC channel input header

JP11

ADC chip-select header

JP12

EEPROM VDD header

JP13

EEPROM chip-select header

JP16

ADC RST header

JP17

Event counter input header

JP18

RTR button header

JP19

SPI monitor chip-select input header

JP21

ADC SPI header

JP22

VIO header

R18

Potentiometer

S1

RESET button

S2

RTR button

S3

EVENT button

Figure 19. CP2130 Evaluation Board with Default Shorting Blocks Installed

TO CP2400 AB LCD

VIO

ADC

AIN0

AIN1

AIN2

AD

C

ADC

EEPROM

VIO

CS2

EEPROM

RTR

BUTTON

POT

TEMP

CLKOUT

CLKOUT

EVTCNTR

BUTTON

CS0

VDD

VIO

MOSI

MISO

VDD

VREGIN

VBUS

RESET SLAVE

GPIO7

CP2130

LOOPBACK

MOSI

SCK

MISO

CS2

CS1

CS0

D11

D10

S1

S2

S3

D9

D8

D7

D6

D5

D4

D3

D2

D1

RTR

EVENT

U1

U4

U2

J6

SILICON LABS

www.silabs.com

JP22

JP16

JP6

JP13

JP12

JP18

JP11

JP9

JP1

JP17

JP3

JP19

J4

JP21

JP10

J5

RESET

R18

CP2130 EB

GND

VDD

VIO

VDDSW

VREGIN

VBUS

SCK

MOSI

MISO

GND

JP4

JP5

SP

I M

O

N

IT

O

R

J3

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Summary of Contents for CP2130

Page 1: ...face Specification Describes the USB control and bulk transfers for CP2130 devices as well as GPIO configuration 4 Software Setup The Software Development Kit SDK for the CP2130 Evaluation Kit is included on the kit DVD The latest version of this installer can also be downloaded from the www silabs com cp2130ek web site This package includes Documentation data sheet application notes user s guide ...

Page 2: ...he CP2130 Evaluation Board to a PC as shown in Figure 1 2 Connect one end of the mini USB cable to a USB Port on the PC 3 Connect the other end of the mini USB cable to the mini USB connector on the CP2130 Evaluation Board Figure 1 Hardware Setup Mini USB Cable ...

Page 3: ...appears as a Silicon Labs CP2130 USB to SPI Bridge in Device Manager as shown in Figure 2 Figure 2 CP2130 in Device Manager 7 CP2130 Software Interface The SLAB_USB_SPI interface library is provided to interface between the user application and USB to control the CP2130 The SLAB_USB_SPI interface library documentation describes the API software functions that can be used to read or write SPI data ...

Page 4: ...ctive LED on the CP2130 Evaluation Board will turn on After a few seconds of inactivity the green Active LED may turn off and the red Suspend LED will then turn on to indicate that the device has entered USB suspend mode This is part of a power saving feature called USB selective suspend 2 Launch the CP2130 Demo application which is found by clicking Start All Programs Silicon Laboratories CP2130 ...

Page 5: ...CP2130 EK Rev 0 2 5 5 Connect to the CP2130 USB to SPI bridge by selecting the device in the Device Selection combo box and clicking the Connect button Figure 4 Connecting to a CP2130 Evaluation Board 5 ...

Page 6: ...isplayed in the Potentiometer Voltage gauge Rotate the potentiometer and watch the voltage change 7 Observe the temperature sensor value displayed in the Temperature Sensor gauge Figure 5 Reading the Potentiometer and Temperature Sensor ADC Channel Inputs 6 7 ...

Page 7: ... write and read b Click the Run Speed Test button to run a short throughput test using the selected transfer mode or click the Continuous checkbox and then click Run Speed Test to run a continuous throughput test Click Stop Speed Test to cancel a continuous throughput test c Observe the throughput measurement in the SPI Throughput gauge Figure 6 Running SPI Throughput Tests 8a 8b 8c ...

Page 8: ...up to VIO or driven low When the GPIO pin is configured for Push Pull mode the pin is driven either high or low b Read the current state of the GPIO pin latch from the Logic Level text field c Toggle the GPIO pin latch value by clicking the Drive High Drive Low button Clicking Drive High will set the latch value to 1 Clicking Drive Low will set the latch value to 0 Observe the new latch value by r...

Page 9: ...PROM a Enter a string into the Write text box Click the Write button to write the string to the external EEPROM b Click the Read button to read the string from the external EEPROM and display the string in the Read text box Figure 8 Reading and Writing the SPI EEPROM 10a 10b ...

Page 10: ...d to GPIO 4 CS4 EVTCNTR a Press the EVENT button on the CP2130 Evaluation Board Notice that the Event Counter Counts field updates to reflect the total number of button presses b Click the Reset button in the application to clear the event count back to zero Figure 9 Monitoring Push Button Presses Using the Event Counter 11a 11b ...

Page 11: ...ls to plot The following ADC channels are available Potentiometer CH 0 Temp Sensor CH 1 or CH 2 By default Channel 2 is connected to GPIO 5 CS5 CLKOUT Other analog signals may be connected to any of the ADC analog inputs and plotted using the plot window c View the graph of the selected ADC input channel Figure 10 Plotting ADC Sample Values 12a 12b 12c ...

Page 12: ...een Active LED on the CP2130 Evaluation Board will turn on After a few seconds of inactivity the green Active LED may turn off and the red Suspend LED will then turn on to indicate that the device has entered USB suspend mode This is part of a power saving feature called USB selective suspend 2 Launch the CP2130 Evaluation Tool application which is found by clicking Start All Programs Silicon Labo...

Page 13: ...al string f Release Version The CP2130 USB BCD device release number g Manf The CP2130 USB manufacturer string h Product The CP2130 USB product string i CLKOUT Divider The GPIO 5 CS5 CLKOUT clock output frequency divider value When GPIO 5 is configured for CLKOUT mode this divider is used to control the output frequency The CLKOUT divider reset value is stored in the one time programmable ROM but ...

Page 14: ...s the timeout for SPI transfer operations in milliseconds If the specified total number of bytes isn t read or written in the time specified the operation will timeout and abort iii Poll RTR Block Size For an asynchronous read and a read with RTR the poll RTR block size specifies the number of bytes to read from the library buffer during each poll interval period iv Poll Interval ms For asynchrono...

Page 15: ...CP2130 EK Rev 0 2 15 Figure 13 Configuring an SPI Transfer 6a 6b 6c ...

Page 16: ...te values into the Transmit Data text box and send the data in the write transfer ii Sequence Write sequential data starting from 0x00 to 0xFF and repeat until the specified number of bytes are written iii Random Write random data until the specified number of bytes are written d Click the Execute SPI Transfer button to start the WriteRead SPI transfer e The data being read will be displayed in th...

Page 17: ...lick the Execute SPI Transfer button to start the asynchronous read transfer The button will change to Abort Read Operation while the transfer is in progress This button can be clicked to abort the current read before the timeout elapses or the total number of bytes is read d The received data will be displayed in the Receive Data text box when the application reads the poll block size every poll ...

Page 18: ...mmand it will perform a reset and re enumerate on the bus 10 GPIO pins configured as GPIO outputs can controlled using the GPIO Toggle buttons Click the GPIO pin 0 10 button to toggle the output latch value GPIO pins not configured as GPIO outputs are grayed out Figure 16 Resetting the Device and Toggling GPIO Pins 9 10 ...

Page 19: ...also contains two SPI slave devices an Si8902 Isolated Monitoring ADC and a 256 x 8 SPI EEPROM Figure 17 and Figure 18 highlight the CP2130 Evaluation Board features Figure 17 CP2130 Evaluation Board Features Front LEDs Potentiometer ADC Headers Temperature Sensor Mini USB Connector Reset Push Button CP2130 Port Access SPI Monitor Power and SPI Test Points CP2400 AB LCD Header Push Button Switches...

Page 20: ...CP2130 EK 20 Rev 0 2 Figure 18 CP2130 Evaluation Board Features Back EEPROM ADC ...

Page 21: ... JP11 ADC chip select header JP12 EEPROM VDD header JP13 EEPROM chip select header JP16 ADC RST header JP17 Event counter input header JP18 RTR button header JP19 SPI monitor chip select input header JP21 ADC SPI header JP22 VIO header R18 Potentiometer S1 RESET button S2 RTR button S3 EVENT button Figure 19 CP2130 Evaluation Board with Default Shorting Blocks Installed TO CP2400 AB LCD VIO ADC AI...

Page 22: ...r the SPI monitor pin definitions 10 4 Mini Universal Serial Bus USB Connector J5 A Mini Universal Serial Bus USB connector J5 is provided to facilitate connections to the USB interface on the CP2130 See Table 2 for the USB pin definitions Table 1 SPI Monitor Pin Definitions Pin Definition 1 No Connect 2 GND 3 No Connect 4 No Connect 5 MISO 6 No Connect 7 SCK 8 MOSI 9 SPI_MON_CS See Section 10 17 ...

Page 23: ...nal voltage regulator is disabled and an external supply voltage must be connected to the VDD test point Do not exceed the maximum VDD voltage specification USB bus powered mode Short Pins 2 3 on JP1 VREGIN is shorted to VBUS and the CP2130 internal voltage regulator is enabled The board VDD is powered by the CP2130 internal voltage regulator output See Table 4 for the VREGIN input header pin defi...

Page 24: ...tion See Table 6 for the SPI loopback header pin definitions 10 9 ADC VDD Header JP9 This header provides access to the ADC VDD pin Install a shorting block on JP9 to provide power to the ADC from VIO See Table 7 for the ADC VDD header pin definitions Table 5 JP3 JP4 and JP5 LED Header Locations GPIO Pin LED Pins GPIO 0 CS0 D1 JP3 1 2 GPIO 1 CS1 D2 JP3 3 4 GPIO 2 CS2 D3 JP3 5 6 GPIO 3 CS3 RTR D4 J...

Page 25: ...the EEPROM from VIO See Table 10 for the EEPROM VDD header pin definitions 10 13 EEPROM Chip Select Header JP13 This header provides access to the EEPROM chip select pin Install a shorting block on JP13 to connect the CP2130 CS2 pin to the EEPROM chip select pin See Table 11 for the EEPROM chip select header pin definitions Table 8 ADC Channel Input Header Locations Analog Source Analog Input Pins...

Page 26: ...5 CLKOUT Short Pins 2 3 on JP17 Count events from the GPIO 5 CS5 CLKOUT signal See Table 13 for the event counter input header pin definitions 10 16 RTR Button Header JP18 This header provides access to the RTR button signal Install a shorting block on JP18 to connect the RTR button to the CP2130 GPIO 3 CS3 RTR pin See Table 14 for the RTR button header pin definitions Table 12 ADC Reset Header Pi...

Page 27: ...blocks to connect each SPI signal to the appropriate CP2130 SPI pin Table 16 lists the ADC SPI signals corresponding to each header position 10 19 VIO Header JP22 This header provides access to the CP2130 VIO pin Install a shorting block on JP22 short VIO to VDD See Table 17 for the VIO header pin definitions Table 15 SPI Monitor Chip Select Input Header Pin Definitions SPI_MON_CS Pins CS0 JP19 1 ...

Page 28: ... C24 1uF J5 USB TYPE MINI B V D D ID GND SH SH C27 4 7uF D13 SP0503BAHT JP22 R34 33 C26 4 7uF JP1 TP18 NI R37 33 C23 0 1uF C22 1uF R35 47K RESET NI GND R36 47K U1 CP2130 VDD 6 VIO 5 REGIN 7 GND 2 RESET 9 GPIO 5_CS5_CLKOUT 17 VBUS 8 D 3 D 4 GPIO 4_CS4_EVTCNTR 18 GPIO 3_CS3 19 GPIO 0_CS0 22 GPIO 2_CS2 20 MOSI 23 GPIO 1_CS1 21 MISO 24 SCK 1 GPIO 10_CS10_SUSPEND 11 GPIO 9_CS9_SUSPEND 12 GPIO 8_CS8_SPI...

Page 29: ...LK NSS RST Switched VIO Supply R6 470 C7 1uF U3 25AA02E48 CS 1 MISO 2 MOSI 5 SCLK 6 WP 3 GND 4 HOLD 7 VCC 8 D5 GPIO4 R30 0 R14 470 JP18 RTR JP11 C1 1uF C28 1uF NI R5 470 J4 SPI MONITOR 1 3 5 2 4 6 7 8 9 10 R12 1K C14 0 1uF D3 GPIO2 JP13 R3 470 R39 0 R13 1K R10 470 D11 RED SUSPEND R23 1K R41 0 R28 0 R11 470 U4 MCP9701AT GND 3 VDD 1 VOUT 2 M1 NTR4171PT1G GND D4 GPIO3 R4 470 S1 RESET JP4 R32 33 R18 1...

Page 30: ...D12 BAT54C Fairchild BAT54C 30 V Dual Schottky SOT23 AAK D13 SP0503BAHTG Littlefuse SP0503BAHT 20 V TVS SOT143 AKKK JP1 JP17 TSW 103 07 T S Samtec HEADER 1x3 Header CONN 1X3 JP3 TSW 109 01 T D Samtec Header 0 1in 2X9 Header CONN2X9 JP4 JP5 JP6 JP9 JP11 JP12 JP13 JP16 JP18 JP22 TSW 102 07 T S Samtec JUMPER Header CONN1X2 JP10 JP19 JP21 TSW 103 07 T D Samtec HEADER 2x3 Header CONN2X3 JS1 JS2 JS3 JS4...

Page 31: ... 4702F Venkel 47 k 1 ThickFilm R0402 R42 CR0603 10W 2000F Venkel 200 1 ThickFilm R0603 SF1 SF2 SF3 SF4 SJ61A6 3M BUMPER RUBBER_FOOT_SMALL S1 S2 S3 EVQ PAD04M PANASONIC CORP MOMENTARY Tactile SW4N6 5X4 5 PB TP2 TP3 TP4 151 207 RC Kobiconn RED Loop TESTPOINT U1 CP2130 F01 GM SiLabs CP2130 MCU QFN24N4X4P0 5 U2 74AUP1G125GW NXP 74AUP1G125 1 2 to 3 6 BUFFER SOT353 5N U3 25AA02E48 I SN Microchip 25AA02E...

Page 32: ...sumes no responsibility for errors and omissions and disclaims responsibility for any consequences resulting from the use of information included herein Additionally Silicon Laboratories assumes no responsibility for the functioning of undescribed fea tures or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warran ty represent...

Page 33: ...андарту ISO 9001 Лицензия ФСБ на осуществление работ с использованием сведений составляющих государственную тайну Поставка специализированных компонентов Xilinx Altera Analog Devices Intersil Interpoint Microsemi Aeroflex Peregrine Syfer Eurofarad Texas Instrument Miteq Cobham E2V MA COM Hittite Mini Circuits General Dynamics и др Помимо этого одним из направлений компании ЭлектроПласт является на...

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