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CPU to PCI Write Buffer
When enable this, up to four words of data can be written to PCI bus
without interrupting CPU. When disabled this, a write buffer is not used
and the CPU read cycle will not be completed until PCI bus signals that
it is ready to receive the data.
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The choice: Enabled, Disabled.
PCI Dynamic Bursting
When enable this, up to four words of data can be written to PCI bus
without interrupting CPU. When disabled this, a write buffer is not used
and the CPU read cycle will not be completed until PCI bus signals that
it is ready to receive the data.
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The choice: Enabled, Disabled.
PCI Master 0 WS Write
When enable this, writes to PCI bus are executed with zero wait state.
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The choice: Enabled, Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Enable it to support compliance with PCI
specification version 2.1.
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The choice: Enabled, Disabled.
PCI #2 Access #1 Retry
When enable it, AGP Bus (PCI#1) access to PCI Bus (PCI#2) is executed
with error retry feature.
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The choice: Enabled, Disabled.
AGP Master 1 WS Write
This implements a single delay when writing to AGP Bus. Usually, two-
wait states is used by system, which is default setting for greater stability.
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The choice: Enabled, Disabled.
AGP Master 1 WS Read
This implements a single delay when reading to AGP Bus. By default,
two-wait states are used by the system, allowing for greater stability.
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The choice: Enabled, Disabled.
Memory Parity ECC Check
This item allows users to enable memory error correcting code (ECC)
function. Meanwhile, SDRAM modules with ECC installed is necessary.
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The choice: Auto, Disabled.
