Sharp UX-A1000, Service Manual

Page: 57 / 128

UX-A1000U
[2] Circuit description of control PWB
1. General description
Fig. 2 shows the functional blocks of the control PWB, which is com-
posed of 5 blocks.
Fig. 2 Control PWB functional block diagram
2. Description of each block
(1) Main control block
The main control block is composed of CONEXANT 1 chip fax engine
(SCE214V), FLASH (4Mbit x 2), DRAM (16Mbit), ASIC (
µ
PD65944).
Devices are connected to the bus to control the whole unit.
1) SCE214V (IC16) : pin-176 QFP (FAX CONTROLLER)
1 chip fax engine has internal integrated analog (20438) and internal
memory (SRAM : 32kbit).
2) Pm39LV040-70VC (IC5, 6): pin-32 TSOP (FLASH)
(IC5)FLASH of 4Mbit equipped with software for the main CPU.
(IC6)FLASH of 4Mbit equipped with MEMORY for registration data.
3) IS41LV8205 (IC4): pin-28 SOJ (DRAM)
Image memory for recording process.
• Memory for recording pixel data without paper.
• Memory for system work and ECM receive buffer.
4)
µ
PD65944 (IC12): pin-100 QFP (ASIC)
ASIC between SCE214V and Hurricane.
It converts the resolution and the aspect ratio of the serial scanning data
sent by SCE214V and sends the converted data to Hurricane by parallel
IF.
5) MSM51V4800E (IC19): pin-28 SOJ (DRAM)
Dedicated image buffer for ASIC (IC12).
5 – 2
(1) SCE214V
IA(CX20438)
MEMORY(SRAM)
(2) FLASH
(4) ASIC (5) DRAM
(3) DRAM
(2) IC16 (SCE214V) Hardware description
1) Integrated Controller (SCC)
The Controller contains an internal MC24 Processor with a 16-MB ad-
dress space and dedicated circuitry optimized for facsimile image
processing and monitoring and for thermal or thermal transfer printer
support.
The CPU provides fast instruction (up to 10 MHz clock speed) execu-
tion and memory efficient input/output bit manipulation. The CPU con-
nects to other internal functions over an 8-bit data bus and 24-bit ad-
dress bus and dedicated control lines.
The 24-bit external address bus, 8-bit data bus, control, status and de-
coded chip select signals support connection to external DRAM, and
FLASH memory.
2) DRAM Controller
The CX06835 includes a DRAM controller with signal and page mode
access support which supports fast, normal, or slow refresh time. DRAM
memory space is provided in one block up to 4 MB. A maximum of 4 MB
of DRAM is supported. This space has a programmble size and starting
address. Refresh is performed automatically and is supported in stand-
by mode. CAS and RAS signal support is provided for one-DRAM banks
for both 4-bit and 8-bit organizations. Access speeds from 50ns to 70ns
can be supported.
3) DMA Channels
Six internal DMA channels support memory access for scanner, T.4/T.6,
and resolution conversion. DMA Channel 2 can be reprogrammed for
external access to thermal printing, thermal transfer, or plain paper inkjet
printing.
4) External RAM and ROM
Moveable and programmable size external SRAM memory of up to 1
MB, DRAM memory of up to 4 MB, and ROM of up to 2 MB can be
directly connected to the SCE214V. By using an external address de-
coder, the size of SRAM and/or ROM can be extended. The ROM stores
all the program object code.
5) Flash Memory Controller
The SCE214V includes a flash memory controller that supports NOR,
NAND, and Serial NAND-type flash memory. The supported size of NOR-
type memory is up to 1 MB and the supported size of NAND-type memory
is unlimited.
6) Stepper Motor Control
Eight outputs are provided to external current drivers: four to the scan-
ner motor and four to the printer motor. The stepping patterns are pro-
grammable and selectable line times are supported. A timeout circuit
controls the power control of the motors. The printer or scanner motor
outputs can be programmed as GPOs for applications using single mo-
tor or paper printers.
7) T.4/T.6 Compressor/Decompressor
MH, MR and MMR compression and decompression are provided in
hardware. T.4 line lengths of up to 8192 pixels are supported. MMR and
Alternating Compression/Decompression (ACD) on a line by line basis
provide support for up to three independent compression and decom-
pression processes.
8) Bi-level Resolution Conversion
One independent programmable bi-level 1D-resolution conversion block
is provided to perform expansion or reduction on the T.4 decompressed
data and scan image data. Image expansion can be programmed up to
200% and reduction down to 33%. Vertical line ORing and data output
bit order reversal is also provided.
9) Printer IF
The Printer Interface provides a standard connection between the
SCE214V and a thermal printhead to support thermal printing or thermal
transfer. The thermal printer interface consists of programmable data,
latch, clock, and up to four strobe signals. Programmable timing sup-
ports traditional thermal printers, as well as the latchless split mode print-
ers, and line lengths of up to 2048 pixels. Line times from 5 ms to 40 ms
are supported.
The SCE214V includes a thermal ADC (TADC) function utilizing a D/A
converter and a comparator to monitor the printhead temperature. Ex-
ternal terminating resistors must be supplied; the values are determined
by the specific printhead selected.
As an option, plain paper inkjet printing can be supported.
10) Scanner and Video Control
Five programmable control and timing signals support common CCD
and CIS scanners. The video control function provides signals for con-
trolling the scanner and for processing its video output. Three program-
mable control signals (START, CLK1n, and CLK2) provide timing re-
lated to line and pixel timing. These are programmable with regard to
start time, relative delay and pulse width.
Two video control output signals (VIDCTL[1:0]) provide digital control
for external signal pre-processing circuitry. These signals provide a per
pixel period, or per line period, timing with programmable polarity con-
trol for each signal.