Sharp UP-3300, Service Manual, Page: 48 / 108

Pin
NO.
Name UP-3300 I/O Description
131 /CSC /CS3 IS USART_C chip select
132 TRNDTC TXD3 O RS-232 transmission
data signal
133 /DTRC /DTR3 O RS-232 data terminal
ready signal
134 /RTSC /RTS3 O USART_C
request to send
135 RCVDTC RCVDT3 IS RS-232 reception
data signal
136 /CTSC GND IS GND
137 /DSRC /DSR3 IS RS-232 data set
ready signal
138 TRNRDYC TRNRDY3 O RS-232 data
transmission enable
signal
139 RCVRDYC RCVRDY3 O RS-232 data
reception enable
signal
140 TRNEMPC TRNEMP3 O RS-232 transmission
buffer empty signal
141 SYCBKC NC IO NC
142 VCC VCC +5V
143 GND GND GND
144 /CSD VCC IS USART_D chip select
145 TRNDTD NC O NC
146 /DTRD NC O NC
147 /RTSD NC O NC
148 RCVDTD GND IS GND
149 /CTSD GND IS GND
150 /DSRD GND IS GND
151 TRNRDYD NC O NC
152 RCVRDYD NC O NC
153 TRNEMPD NC O NC
154 SYCBKD NC IO NC
155 /WIN /WRH I Write signal
156 /RIN /RDH I Read signal
157 RSLCT0 AH0 I Address bus
158 RSLCT1 AH1 I Address bus
159 RST RES USART IS Reset signal
160 MCLK CLK USART I
I TTL input
ID TTL input with pull down
IS TTL Schmidt input
ISU TTL Schmidt input with pull up
IO TTL I/O
3S 3-state Buffer (6mA)
ON6 Open drain (6mA)
2-4. Z80 CPU
1) Features
The extensive instruction set contains 158 instructions, including the
8080A instruction set as a subset.
•
NMOS version for low cost high performance solutions, CMOS
version for high performance low power designs.
•
Z0840006 - 6.17 MHz
•
CMOS Z84C0006 - DC to 6.17 MHz, Z84C008 - DC to 8 MHz,
Z84C0010 - DC to 10 MHz, Z84C0020 - DC - 20 MHz
•
6 MHz version can be operated at 6.144 MHz clock.
•
The Z80 microprocessors and associated family of peripherals can
be linked by a vectored interrupt system. This system can be
daisy-chained to allow implementation of a priority interrupt
scheme.
•
Duplicate set of both general-purpose and flag registers.
•
Two sixteen-bit index registers.
•
Three modes of maskable interrupts:
Mode 0 — 8080A similar;
Mode 1 — Non-Z80 environment, location 38H;
Mode 2 — Z80 family peripherals, vectored interrupts.
•
On-chip dynamic memory refresh counter.
Figure 1. Pin functions
2) Pin configuration
44 pin Quad Flat Pack (QFP), Pin Assignments
(Only available for 84C00)
DATA
BUS
ADDRESS
BUS
CPU
CONTROL
CPU
BUS
CONTROL
SYSTEM
CONTROL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D1
D2
D3
D4
D5
D6
D0
D7
M1
MREQ
IORQ
RD
WR
RFSH
HALT
WAIT
INT
NMI
RESET
BUSREQ
BUSACK
CLK
+5V
GND
Z8400
Z80 CPU
A4
A3
A2
A1
A0
GND
RFSH
M1
RESET
NC
A5
D3
D5
D6
+5V
D2
D7
D0
D1
NC
CLK
D4
1
11
33
23
22 12
34 44
Z80 CPU
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