b. Memory
Map
Description
Size
Address range
Note
DRAM
Bank 0
8MBytes
00000000H-007FFFFFH
Standard
Bank
0a
4MBytes
00000000H-003FFFFFH
Bank
0b
4MBytes
00400000H-007FFFFFH
Bank 1
4MBytes
00800000H-00BFFFFFH
Not used
Bank 2
4MBytes
00C00000H-00FFFFFFH
Bank 1
8MBytes
00800000H-00FFFFFFH
Bank 2
8MBytes
01000000H-017FFFFFH
Bank 1
16MBytes
00800000H-017FFFFFH
Standard
Bank 2
16MBytes
01800000H-027FFFFFH
Option
ROM
Bank 2(CS2)
4MBytes
1FC00000H-1FFFFFFFH
Flash memory (PS)(Japan) ROM
(PCL) (EX)
Bank 1(CS1)
8MBytes
1F400000H-1FBFFFFFH
Flash memory
Bank 0(CS0)
8MBytes
1EC00000H-1F3FFFFFH
Flash memory
IO channel 0 (Bi-Parallel I/F)
R3741
16MBytes
08000000H-08FFFFFFH
IO channel 1 (Reserved)
EXternal I/O #1
16MBytes
09000000H-09FFFFFFH
IO channel 2 (Reserved)
Miscellaneous
16MBytes
0B000000H-0BFFFFFFH
IO channel 3 (Apple Talk & RS232C)
External I/O #0
256MBytes
0C000000H-1BFFFFFFH
Centronics (Internal)
1MByte
0A000000H-0A0FFFFFH
Engine Control (Internal/Video I/F)
1MByte
0A000000H-0A0FFFFFH
Typhoon address space (Not used)
Internal Registers (Not used)
16MBytes
1D000000H-1DFFFFFFH
R3741 (IEEE-P1284) Register
Address
R/W
Port Bit
Signal Name
Description
08000000H
R/W
7
HBDA
Enter Host Busy Data Available
0 - Enter HBPA via interrupt phase
1 - Enter HBPA directly
6
Count
Host Timeout Counter Enable
0 - Clear Count
1 - Enable Counter
5
RegBusy
Register Busy
0 - Not Busy
1 - Busy
4
Timeout
Written by CPU to indicate the Host TimeOut
Counter has reached 1 second.
Cleard automatically when the Host returns to Compatibility
3,,2
1284 Mode
Indicates IEEE 1284 Mode
0 - Compatible Mode
1 - Nibble Mode or Nibble ID
2 - Byte Mode or Byte ID
3 - ECP Mode or ECP ID
1
DevID
Device ID Byte or Nibble Mode
0 - Not Device ID Byte or Nibble Mode
1 - Device ID Byte or Nibble Mode
0
IPrime
IPrime (Init) pulse detected
0 - IPrime not detected
1 - IPrime detected
SHARP SERVICE MANUAL JX8200SM [13] ELECTRICAL SECTION
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