Pin Name
Pull Up/
Pull Dn
(1)
Type
Description
TDS
∗
R3710
only: O
R3740
only: I/O
Typhoon Data Strobe:
Master mode (input) – during Write indicates that there is valid data on the A/D bus. During
Read indicates data phase.
Slave mode (output) – the R3710 or R3740 drives TDS
∗
to indicate that it is ready to accept
data during reads or that valid data is available during write on the A/D bus.
TDTACK
∗
P.U.
(R3710 only)
I/O
Typhoon Data Acknowledge:
Master mode (output) – The R3710 or R3740 asserts TDTACK
∗
to indicate that the system is
receiving or driving the requested data to/from the A/D bus.
Slave mode (input) – The Typhoon asserts TDTACK
∗
to signal that it has supplied or received
data on its bus.
TAACK
∗
O
Typhoon Address Acknowledge: The R3710 or R3740 asserts TAACK
∗
in the same clock
that it asserts ALE for the Typhoon. This insures that the Typhoon continues driving the
address until latched by the system.
TCS
∗
O
Typhoon Chip Select: When the CPU accesses the Typhoon, the R3710 or R3740 asserts
TCS
∗
. It is active one clock before R3710 or R3740 asserts TAS
∗
.
TADOE
∗
O
Typhoon A/D Output Enable: The R3710 or R3740 asserts TADOE
∗
when the Typhoon
drives the address to the A/D bus, and in the data phases of the Typhoon.
TADDIR
∗
O
Typhoon A/D Direction: The R3710 or R3740 asserts TADDIR
∗
(LOW) when the Typhoon
drives the A/D bus.
TATOE
∗
O
Typhoon Address To Output Enable: The R3710 or R3740 asserts TATOE
∗
in the address
phase of cycles in which the CPU accesses the Typhoon.
Buffer Control
OEMAD
∗
O
Output Enable between Memory and A/D: Output enable for the data path transceiver
between the memory system (ROM and DRAM) and the A/D bus.
I/O Bus
IODATA[15:0]
P.U.
(R3710 only)
I/O
Input/Output Devlce Data: Bidirectional 16-bit I/O Data bus.
IORD
∗
O
Input/Output Device Read: Active during Read from an I/O device.
IOWR
∗
O
Input/Output Device Write: Active during Write to an I/O device.
IOCS
∗
[1:0]
O
Input/Output Device Chip Select: Chip selects for 8 bit I/O channels 0 and 1.
IOGPCS
∗
[1:0]
O
Input/Output Device Chip Select: Chip selects for 16 bit I/O channels 0 and 1.
DMAREQ[1:0]
P.D.
(R3710 only)
I
DMA Request: Requesting DMA service on 8-bit channels 0 and 1.
DMAACK
∗
[1:0]
O
DMA Acknowledge: Indicating that DMA access is granted on 8-bit channels 0 and 1.
IOA1
O
Input/Output Devlce Address bit 1: Provides a half word (16 bit) address on the I/O bus.
IOBE
∗
[1:0]
O
Input/Output Device Byte Enable: Indicates which byte data bus is valid on the 16 bit I/O bus.
IOBE
∗
[1] corresponds to IODATA[15:8] and IOBE[0] corresponds to IODATA[7:0].
IOWAIT
∗
P.U.
I
Input/Output Device Wait: Indicates to the R3710 or R3740 that a transfer cycle on the I/O
bus needs to be extended.
PIO[5:0]
P.U.
(R3710 only)
I/O
Programmable Input/Output: Individually programmed pins for inputs, interrupt inputs or
outputs.
Bidirectional Centronics
CWOE
∗
O
Centronics Write Output Enable: Controls the data register Enable signal from the printer to
the host.
CROE
∗
O
Centronics Read Output Enable: Controls the OE
∗
of the Centronics external register in the
direction from the host to the printer (the IODATA[7:0] bus).
CWSTROBE
O
Centronics Write Strobe: Clocks data from IODATA[7.0] into the Centronics register (from
printer to host).
CRSTROBE
O
Centronics Read Strobe: Clocks data from the host into the Centronics register (from host to
printer).
CSTROBE
∗
P.U.
I
Centronics Strobe: Host driven.
NOTE: This is
the Compatibility
Mode Name.
SHARP SERVICE MANUAL JX8200SM [13] ELECTRICAL SECTION
13 – 9
