i. OCTAL REGISTERED TRANSCEIVERS
I.
BLOCK DIAGRAM
II.
PIN CONFIGURATIONS
III.
PIN DESCRIPTION
Name
I/O
Description
A0
∼
7
I/O
Eight bidirectional lines carrying the A Register
inputs or B Register outputs.
B0
∼
7
I/O
Eight bidirectional lines carrying the B Register
inputs or A Register outputs.
CPA
I
Clock for the A Register. When CEA is LOW,
data is entered into the A Register on the LOW-
to-HIGH transition of the CPA signal.
CEA
I
Clock Enable for the A Register. When CEA is
LOW, data is entered into the A Register on the
LOW-to-HIGH transition of the CPA signal. When
CEA is HIGH, the A Register holds its contents,
regardless of CPA signal transitions.
OEB
I
Output Enable for the A Register. When OEB is
LOW, the A Register output are enabled onto the
B0-7 lines. When OEB is HIGH, the B0-7 outputs
are in the high-impedance state.
CPB
I
Clock for the B Register. When CEB is LOW,
data is entered into the B Register on the LOW-
to-HIGH transition of the CPB signal.
CEB
I
Clock Enable for the B Register. When CEB is
LOW, data is entered into the B Register on the
LOW-to-HIGH transition of the CPB signal. When
CEB is HIGH, the B Register holds its contents,
regardless of CPB signal transitions.
OEA
I
Output Enable for the B Register. When OEA is
LOW, the B Register output are enabled onto the
A0-7 lines. When OEA is HIGH, the A0-7 output
are in the high-impedance state.
IV.
REGISTER FUNCTION TABLE(1)
(Applies to A or B Register)
Inputs
Internal
Q
Function
D
CP
CE
X
X
H
NC
Hold Data
L H
↑
↑
L
L
L
H
Load Data
NOTE: 1. H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Don’t Care
NC = No Change
↑
= LOW-to-HIGH Transition
V.
OUTPUT CONTROL(1)
OE
Internal
Q
Y-Outputs
Function
52/2052
53
H
X
Z
Z
Disable Outputs
L
L
L
H
L
H
H
L
Enable Outputs
NOTE: 1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
OEB
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
CPA
CEA
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
CE CP
A
Reg.
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
B
Reg.
CE CP
CPB
CEB
OEA
B7
1
VCC
24
B6
2
A7
23
B5
3
A6
22
B4
4
A5
21
B3
5
A4
20
B2
6
A3
19
B1
7
A2
18
B0
8
A1
17
OEB
9
A0
16
CPA
10
OEA
15
CEA
11
CPB
14
GND
12
CEB
13
P24-1
D24-1
SO24-2
SO24-7*
SO24-8*
&
E24-1
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
* For 29FCT52/29FCT2052AT/BT/CT only
B4
5
A5
25
B3
6
A4
24
B2
7
A3
23
NC
8
NC
22
B1
9
A2
21
B0
10
A1
20
OEB
11
A0
19
CP
A
12
B5
4
CE
A
13
B6
3
GN
D
14
B7
2
NC
15
NC
1
CE
B
16
VC
C
28
CP
B
17
A7
27
OE
A
18
A6
16
INDEX
L28-1
LCC
TOP VIEW
SHARP SERVICE MANUAL JX8200SM [13] ELECTRICAL SECTION
13 – 17