II.
Signal list (Pin configurations)
Vss
Vcc
Clkln
Rsvd(4)
Rsvd(3)
Rsvd(2)
Rsvd(1)
CohReq
Int(5)
Vss
Vcc
SInt(2)
SBrCond(3)
NC
Vss
Vcc
Vss
Vcc
Vcc
Vss
Vss
Vcc
A/D(0)
Int(4)
Int(3)
SInt(1)
SInt(0)
SBrCond(2)
A/D(1)
A/D(2)
A/D(3)
A/D(4)
A/D(5)
A/D(6)
A/D(7)
A/D(8)
A/D(9)
A/D(10)
A/D(11)
A/D(12)
A/D(13)
A/D(14)
A
/D
(31)
Vs
s
Vc
c
Vcc
Vss
A
/D
(30)
A
/D
(29)
A/
D
(2
8
)
A/
D
(2
7
)
A/
D
(2
6
)
A/
D
(2
5
)
A/
D
(2
4
)
A/
D
(2
3
)
A/
D
(2
2
)
A
/D
(21)
A
/D
(20)
A
/D
(19)
A
/D
(18)
A
/D
(17)
A
/D
(16)
A
/D
(15)
B
rC
ond(
0
)
Bu
sR
e
q
Rd
CE
n
Ack
Bu
sErro
r
R
e
se
t
Bu
sG
n
t
SysC
lk
Vss
Vcc
Da
ta
E
n
Wr
Rd
AL
E
D
iag(
0)
/I
v
d
R
rq
D
iag(
1)
Vss
Vcc
A
d
d
r(2
)
A
d
d
r(3
)
Bu
rs
t/
W
rN
e
a
r
12
54
75
84
1
33
84-Pin MQUAD/PLCC
Top View
(PIN DESCRIPTION)
PIN NAME
I/O
DESCRIPTION
A/D (31:0)
I/O
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction in one phase,
and which is used to transmit data between the CPU and external memory resources during the rest of the transfer.
Bus transactions on this bus are logically separated into two phases: during the first phase, information about the
transfer is presented to the memory system to be captured using the ALE output. This information consists of:
Address
(31:4):
The high-order address for the transfer is presented on A/D (31:4).
BE (3:0):
These strobes indicate which bytes of the 32-bit bus will be involved in the transfer, and are
presented on A/D (3:0).
During write cycles, the bus contains the data to be stored and is driven from the internal write buffer. On read cycles,
the bus receives the data from the external resource, in either a single data transaction or in a burst of four words, and
places it into the on-chip read buffer.
During cache coherency operations, the R3081 monitors the A/D bus at the start of a DMA write to capture the write
target address for potential data cache invalidates.
Addr (3:2)
O
Low Address (3:2) A 2-bit bus which indicates which word is currently expected by the processor. Specifically, this two
bit bus presents either the address bits for the single word to be transferred (writes or single datum reads) or functions
as a two bit counter starting at ‘00’ for burst read operations.
During cache coherency operations, the R3081 monitors the Addr bus at the start of a DMA write to capture the write
target address for potential data cache invalidates.
Diag (1)
O
Diagnostic Pin 1. This output indicates whether the current bus read transaction is due to an on-chip cache miss, and
also presents part of the miss address. The value output on this pin is multiplexed:
Cached:
During the phase in which the A/D bus presents address information, this pin is active HIGH
output which indicates whether the current read is a cache miss.
Miss Address (3):
During the remainder of the read operation, this output presents address bit (3) of the address
the processor or was attempting to reference when the cache miss occurred. Regardless of
whether a cache miss is being processed, this pin reports the transfer address during this time.
On write cycles, this output signals whether the data being written as retained in the on-chip data cache. The value of
this pin is multiplexed:
Cached:
During the address phase of write transactions, this signal is an active high output which
indicates that the store data was retained in the on-chip data cache.
Reserved:
The value of this pin during the data phase of writes is reserved.
Diag (0)
O
Diagnostic Pin 0. This output distinguishes cache misses due to instruction references from those due to data
references, and presents the remaining bit of the miss address. The value output on this pin is also multiplexed:
I/D:
If the "Cached" Pin indicates a cache miss, then a high on this pin at this time indicates an
instruction reference, and a low indicates a data reference. If the read is not due to a cache miss
but rather an uncached reference, then this pin is undefined during this phase.
Miss Address (2):
During the remainder of the read operation, this output shows address bit (2) of the address the
processor was attempting to reference when the cache miss occurred. Regardless of whether a
cache miss is being processed, this pin reports the transfer address during this time.
During write cycles, the value of this pin during both the address and data phases is reserved.
SHARP SERVICE MANUAL JX8200SM [13] ELECTRICAL SECTION
13 – 4
