HT-DV40H
8 – 11
R_CS4_B/GPIO
76
Input/Output
ROM / SRAM / flash chip select #4 or GPIO
R_CS3_B/GPIO
77
Input/Output
ROM / SRAM / flash chip select #3 or GPIO
R_CS2_B/GPIO
78
Input/Output
ROM / SRAM / flash chip select #2 or GPIO
R_CS1_B/GPIO
79
Input/Output
ROM / SRAM / flash chip select #1 or GPIO
RST_B
80
Input
System reset (active low reset)
IR_IN/GPIO
81
Input/Output
GPIO
VFD_CLK/GPIO
82
Input/Output
GPIO[21] for VFD_CLK
VFD_STB/GPIO
83
Input/Output
GPIO[22] for VFD_STB
VFD_DATA/GPIO
84
Input/Output
GPIO[23] for VFD_DATA
R_A0
85
Input/Output
ROM / SRAM / flash address bus bit [0] (256pin package)
Symbol
Pin #
Input/Output
Description
Priority selection
Function
Dir
gpio_first[1][0] = 1
GPIO[16]
Input/Output
sft_cfg1[3] = 1'b1
R_CS4_B (default)
Output
sft_cfg13[3:0] = 4'b0111
IEC_RX
Input
sft_cfg13[8:4] = 5'b00110
ADC_DATA
Input
sft_cfg13[11:9] = 3'b001
AT_ADR[2]
Output
sft_cfg13[11:9] = 3'b011
AT_DMARQ
Input
{sft_cfg20[0],sft_cfg7[5:4]} = 3'b011
656_DATA[7]
Output
{sft_cfg20[1],sft_cfg19[5:4]} = 3'b011 HD_DATA[7]
Output
{sft_cfg20[2],sft_cfg14[7:6]} = 3'b011 SRGB_DATA[7]
Output
sft_cfg11[5:3] = 3'b011
EXT_TS_CLK
Input
sfg_cfg17[3:0] = 4'b0011
FM_GPIOB[19]
Input/Output
sfg_cfg17[7:7] = 4'b1000
FM_GPIOB[20]
Input/Output
sfg_cfg17[15:12] = 4'b1000
FM_GPIOB[26]
Input/Output
(other)
GPIO[16]
Input/Output
Priority selection
Function
Dir
gpio_first[1][1] = 1
GPIO[17]
Input/Output
sft_cfg1[2] = 1'b1
R_CS3_B (default)
Output
sft_cfg13[3:0] = 4'b1000
IEC_RX
Input
sft_cfg13[8:4] = 5'b00111
ADC_DATA
Input
sft_cfg13[11:9] = 3'b001
AT_ADR[0]
Output
sft_cfg13[11:9] = 3'b011
AT_INTRQ
Input
sft_cfg14[10:8] = 3'b001
TV_HSYNC_SRGB
Output
sft_cfg11[5:3] = 3'b011
TS_FRAME_B
Input/Output
(other)
GPIO[17]
Input/Output
Priority selection
Function
Dir
gpio_first[1][2] = 1
GPIO[18]
Input/Output
sft_cfg1[1] = 1'b1
R_CS2_B (default)
Output
sft_cfg13[8:4] = 5'b01000
ADC_DATA
Input
sft_cfg14[10:8] = 3'b001
TV_VSYNC_SRGB
Output
sft_cfg11[5:3] = 3'b011
TS_GNT_B
Input/Output
(other)
GPIO[18]
Input/Output
Priority selection
Function
Dir
gpio_first[1][3] = 1
GPIO[19]
Input/Output
sft_cfg1[0] = 1'b1
R_CS1_B (default)
Output
sft_cfg13[8:4] = 5'b01001
ADC_DATA
Input
(other)
GPIO[19]
Input/Output
Priority selection
Function
Dir
gpio_first[1][4] = 1
GPIO[20]
Input/Output
sft_cfg8[0] = 1'b1
IR_IN,GPIO[20]
Input
(other)
GPIO[20] (default)
Input/Output
Summary of Contents for HT-DV40H
Page 13: ...HT DV40H 2 6 MEMO ...
Page 15: ...HT DV40H 4 2 IC701 IXA161AW00 PR PB Y S01 Figure 4 2 MAIN BLOCK DIAGRAM 2 2 ...
Page 19: ...HT DV40H 4 6 Figure 4 6 POWER BLOCK DIAGRAM 2 2 ...
Page 30: ...HT DV40H 5 11 MEMO ...
Page 34: ...HT DV40H 6 4 Figure 6 3 MAIN SCHEMATIC DIAGRAM 3 8 TO SUBWOOFER PWB D BI402 13 14 15 16 17 18 ...
Page 35: ...HT DV40H 6 5 Figure 6 4 MAIN SCHEMATIC DIAGRAM 4 8 MIC_IN A B C D E F G H 1 2 3 4 5 6 ...
Page 36: ...HT DV40H 6 6 Figure 6 5 MAIN SCHEMATIC DIAGRAM 5 8 AZ4558CME JP826 7 8 9 10 11 12 ...
Page 38: ...HT DV40H 6 8 Figure 6 7 MAIN SCHEMATIC DIAGRAM 7 8 AUDIO SIGNAL A B C D E F G H 1 2 3 4 5 6 ...
Page 39: ...HT DV40H 6 9 Figure 6 8 MAIN SCHEMATIC DIAGRAM 8 8 SPEAKER TERMINAL 7 8 9 10 11 12 ...
Page 40: ...HT DV40H 6 10 Figure 6 9 USB SCHEMATIC DIAGRAM BI706 A B C D E F G H 1 2 3 4 5 6 ...
Page 41: ...HT DV40H 6 11 MEMO ...
Page 45: ...HT DV40H 6 15 Figure 6 13 DISPLAY SCHEMATIC DIAGRAM 2 2 7 8 9 10 11 12 ...
Page 47: ...HT DV40H 6 17 MEMO ...
Page 49: ...HT DV40H 6 19 Figure 6 16 DVD SCHEMATIC DIAGRAM 2 8 7 8 9 10 11 12 ...
Page 52: ...HT DV40H 6 22 Figure 6 19 DVD SCHEMATIC DIAGRAM 5 8 7 8 9 10 11 12 ...
Page 54: ...HT DV40H 6 24 Figure 6 21 DVD SCHEMATIC DIAGRAM 7 8 CD SIGNAL A B C D E F G H 1 2 3 4 5 6 ...
Page 67: ...HT DV40H 6 37 Figure 6 34 WIRING SIDE OF POWER PWB BOTTOM VIEW 2 2 7 8 9 10 11 12 ...
Page 71: ...HT DV40H 6 41 Figure 6 38 WIRING SIDE OF DISPLAY PWB BOTTOM VIEW 2 2 7 8 9 10 11 12 ...