HT-DV40H
8 – 14
GPIO/M_DD[29]
154
Input/Output
SDRAM data bus bit 29 or GPIO[32]
GPIO/M_DD[28]
155
Input/Output
SDRAM data bus bit 29 or GPIO[32]
GPIO/M_DD[27]
157
Input/Output
SDRAM data bus bit 27 or GPIO[34]
Symbol
Pin #
Input/Output
Description
Priority selection
Function
Dir
hw_cfg_chg[5]=1íb1
SDRAM data bus [29]
Input/Output
gpio_first[2][0] = 1
GPIO[32]
Input/Output
hw_cfg_chg[4] = 1'b1
FL_ROM_DATA[13]
Input/Output
sft_cfg2[7:6] = 1
UA0_CTS_B
Input
sft_cfg13[14:12] = 3'b001
AT_D[14]
Input/Output
sft_cfg13[14:12] = 3'b100
AT_D[15]
Input/Output
sft_cfg7[11:8] = 4'b0100
VGA_CLK
Input
{sft_cfg20[5:3],sft_cfg14
[15:13]} = 6'b000010
INT0_7
Input
sft_cfg0[13:12] = 1
TV_LCD_R[2]
Output
sfg_cfg15[11:9] = 3'b101
FM_GPIOB[6]
Input/Output
sfg_cfg16[15:12] = 4'b0100
FM_GPIOB[15]
Input/Output
sfg_cfg17[11:8] = 4'b0001
FM_GPIOB[25]
Input/Output
sfg_cfg18[3:0] = 4'b1001
FM_GPIOB[28]
Input/Output
(other)
GPIO[32] (default)
Input/Output
Priority selection
Function
Dir
hw_cfg_chg[5]=1íb1
SDRAM data bus [28]
Input/Output
hw_cfg_chg[5]=1íb1
GPIO[33]
Input/Output
hw_cfg_chg[4] = 1'b1
FL_ROM_DATA[12]
Input/Output
sft_cfg2[7:6] = 1
UA0_RTS_B
Output
sft_cfg13[14:12] = 3'b001
AT_D[1]
Input/Output
sft_cfg13[14:12] = 3'b100
AT_D[1]
Input/Output
sft_cfg1[11:9] = 3'b010
INT1_11
Input
sft_cfg0[13:12] = 1
TV_LCD_R[3]
Output
sfg_cfg15[2:0] = 3'b100
FM_GPIOB[1]
Input/Output
sfg_cfg15[15:12] = 4'b0101
FM_GPIOB[7]
Input/Output
sfg_cfg17[11:8] = 4'b0001
FM_GPIOB[24]
Input/Output
sfg_cfg18[3:0] = 4'b1001
FM_GPIOB[29]
Input/Output
(other)
GPIO[33] (default)
Input/Output
Priority selection
Function
Dir
hw_cfg_chg[5]=1íb1
SDRAM data bus [27]
Input/Output
gpio_first[2][2] = 1
GPIO[34]
Input/Output
hw_cfg_chg[4] = 1'b1
FL_ROM_DATA[11]
Input/Output
sft_cfg2[7:6] = 1
UA0_DSR_B
Input
sft_cfg13[14:12] = 3'b001
AT_D[13]
Input/Output
sft_cfg13[14:12] = 3'b100
AT_D[14]
Input/Output
sft_cfg0[13:12] = 1
TV_LCD_R[4]
Output
sfg_cfg16[3:0] = 4'b0101
FM_GPIOB[8]
Input/Output
sfg_cfg16[15:12] = 4'b0100
FM_GPIOB[14]
Input/Output
sfg_cfg17[11:8] = 4'b0001
FM_GPIOB[23]
Input/Output
sfg_cfg18[3:0] = 4'b1001
FM_GPIOB[30]
Input/Output
(other)
GPIO[34] (default)
Input/Output
Summary of Contents for HT-DV40H
Page 13: ...HT DV40H 2 6 MEMO ...
Page 15: ...HT DV40H 4 2 IC701 IXA161AW00 PR PB Y S01 Figure 4 2 MAIN BLOCK DIAGRAM 2 2 ...
Page 19: ...HT DV40H 4 6 Figure 4 6 POWER BLOCK DIAGRAM 2 2 ...
Page 30: ...HT DV40H 5 11 MEMO ...
Page 34: ...HT DV40H 6 4 Figure 6 3 MAIN SCHEMATIC DIAGRAM 3 8 TO SUBWOOFER PWB D BI402 13 14 15 16 17 18 ...
Page 35: ...HT DV40H 6 5 Figure 6 4 MAIN SCHEMATIC DIAGRAM 4 8 MIC_IN A B C D E F G H 1 2 3 4 5 6 ...
Page 36: ...HT DV40H 6 6 Figure 6 5 MAIN SCHEMATIC DIAGRAM 5 8 AZ4558CME JP826 7 8 9 10 11 12 ...
Page 38: ...HT DV40H 6 8 Figure 6 7 MAIN SCHEMATIC DIAGRAM 7 8 AUDIO SIGNAL A B C D E F G H 1 2 3 4 5 6 ...
Page 39: ...HT DV40H 6 9 Figure 6 8 MAIN SCHEMATIC DIAGRAM 8 8 SPEAKER TERMINAL 7 8 9 10 11 12 ...
Page 40: ...HT DV40H 6 10 Figure 6 9 USB SCHEMATIC DIAGRAM BI706 A B C D E F G H 1 2 3 4 5 6 ...
Page 41: ...HT DV40H 6 11 MEMO ...
Page 45: ...HT DV40H 6 15 Figure 6 13 DISPLAY SCHEMATIC DIAGRAM 2 2 7 8 9 10 11 12 ...
Page 47: ...HT DV40H 6 17 MEMO ...
Page 49: ...HT DV40H 6 19 Figure 6 16 DVD SCHEMATIC DIAGRAM 2 8 7 8 9 10 11 12 ...
Page 52: ...HT DV40H 6 22 Figure 6 19 DVD SCHEMATIC DIAGRAM 5 8 7 8 9 10 11 12 ...
Page 54: ...HT DV40H 6 24 Figure 6 21 DVD SCHEMATIC DIAGRAM 7 8 CD SIGNAL A B C D E F G H 1 2 3 4 5 6 ...
Page 67: ...HT DV40H 6 37 Figure 6 34 WIRING SIDE OF POWER PWB BOTTOM VIEW 2 2 7 8 9 10 11 12 ...
Page 71: ...HT DV40H 6 41 Figure 6 38 WIRING SIDE OF DISPLAY PWB BOTTOM VIEW 2 2 7 8 9 10 11 12 ...
