HT-DV40H
8 – 16
M_DQM3/GPIO
161
Input/Output
SDRAM data input/output mask for M_DD[31:24] , or GPIO[38]
M_DQM2/GPIO
162
Input/Output
SDRAM data input/output mask for M_DD[23:16] , or GPIO[39]
GPIO/M_DD[23]
164
Input/Output
GPIO[40] or SDRAM data bus bit 23
Symbol
Pin #
Input/Output
Description
Priority selection
Function
Dir
sft_cfg0[5]=1’b1
SDRAM data input/output
mask for M_DD[31:24] (default)
Output
gpio_first[2][6] = 1
GPIO[38]
Input/Output
sft_cfg13[3:0] = 4'b1011
IEC_RX
Input
sft_cfg13[8:4] = 5'b01100
ADC_DATA
Input
sft_cfg2[3:2] = 3
UA0_RXD
Input
sft_cfg1[8:6] = 3'b011
FL_MEM_CSALL_B
Output
sft_cfg7[7:6] = 1
FL_PCMCIA_IOW_B
Output
sft_cfg3[13:12] = 2
TV_HSYNC
Input/Output
sft_cfg14[10:8] = 3'b010
TV_HSYNC_SRGB
Output
sft_cfg4[15:13] = 3'b010
TV_HSYNC_PC
Output
sft_cfg7[7:6] = 1
FL_PCMCIA_IOW_B
Output
{sft_cfg20[5:3],sft_cfg14
[15:13]} = 6'b000101
INT0_7
Input
sft_cfg0[13:12] = 1
TV_LCD_G[2]
Output
sfg_cfg16[11:8] = 4'b0101
FM_GPIOB[10]
Input/Output
sfg_cfg16[15:12] = 4'b0100
FM_GPIOB[12]
Input/Output
sfg_cfg17[3:0] = 4'b0001
FM_GPIOB[19]
Input/Output
sfg_cfg18[3:0] = 4'b1001
FM_GPIOB[32]
Input/Output
(other)
GPIO[38]
Input/Output
Priority selection
Function
Dir
sft_cfg0[4]=1’b1
SDRAM data input/output
mask for M_DD[23:16] (default)
Output
gpio_first[2][7] = 1
GPIO[39]
Input/Output
sft_cfg13[8:4] = 5'b01101
ADC_DATA
Input
sft_cfg2[3:2] = 3
UA0_TXD
Output
sft_cfg3[13:12] = 2
TV_VSYNC
Input/Output
sft_cfg14[10:8] = 3'b010
TV_VSYNC_SRGB
Output
sft_cfg4[15:13] = 3'b010
TV_VSYNC_PC
Output
sft_cfg7[7:6] = 1
FL_PCMCIA_IOR_B
Output
sft_cfg1[11:9] = 3'b101
INT1_11
Input
sft_cfg0[13:12] = 1
TV_LCD_G[3]
Output
sfg_cfg15[5:3] = 3'b100
FM_GPIOB[4]
Input/Output
sfg_cfg16[11:8] = 4'b0101
FM_GPIOB[11]
Input/Output
sfg_cfg17[3:0] = 4'b0001
FM_GPIOB[18]
Input/Output
sfg_cfg18[3:0] = 4'b1001
FM_GPIOB[33]
Input/Output
(other)
GPIO[39]
Input/Output
Priority selection
Function
Dir
hw_cfg_chg[5]=1’b1
SDRAM data bus [23]
Input/Output
gpio_first[2][8] = 1
GPIO[40]
Input/Output
sft_cfg13[14:12] = 3'b001
AT_D[11]
Input/Output
sft_cfg13[14:12] = 3'b100
AT_D[12]
Input/Output
{sft_cfg20[0],sft_cfg7[5:4]} =
3'b001
656_DATA[0]
Output
{sft_cfg20[1],sft_cfg19[5:4]} =
3'b001
HD_DATA[0]
Output
{sft_cfg20[2],sft_cfg14[7:6]} =
3'b001
SRGB_DATA[0]
Output
sft_cfg0[13:12] = 1
TV_LCD_G[4]
Output
sfg_cfg16[11:8] = 4'b0100
FM_GPIOB[11]
Input/Output
sfg_cfg16[15:12] = 4'b0101
FM_GPIOB[12]
Input/Output
sfg_cfg17[3:0] = 4'b0001
FM_GPIOB[17]
Input/Output
sfg_cfg18[3:0] = 4'b1001
FM_GPIOB[34]
Input/Output
(other)
GPIO[40] (default)
Input/Output
Summary of Contents for HT-DV40H
Page 13: ...HT DV40H 2 6 MEMO ...
Page 15: ...HT DV40H 4 2 IC701 IXA161AW00 PR PB Y S01 Figure 4 2 MAIN BLOCK DIAGRAM 2 2 ...
Page 19: ...HT DV40H 4 6 Figure 4 6 POWER BLOCK DIAGRAM 2 2 ...
Page 30: ...HT DV40H 5 11 MEMO ...
Page 34: ...HT DV40H 6 4 Figure 6 3 MAIN SCHEMATIC DIAGRAM 3 8 TO SUBWOOFER PWB D BI402 13 14 15 16 17 18 ...
Page 35: ...HT DV40H 6 5 Figure 6 4 MAIN SCHEMATIC DIAGRAM 4 8 MIC_IN A B C D E F G H 1 2 3 4 5 6 ...
Page 36: ...HT DV40H 6 6 Figure 6 5 MAIN SCHEMATIC DIAGRAM 5 8 AZ4558CME JP826 7 8 9 10 11 12 ...
Page 38: ...HT DV40H 6 8 Figure 6 7 MAIN SCHEMATIC DIAGRAM 7 8 AUDIO SIGNAL A B C D E F G H 1 2 3 4 5 6 ...
Page 39: ...HT DV40H 6 9 Figure 6 8 MAIN SCHEMATIC DIAGRAM 8 8 SPEAKER TERMINAL 7 8 9 10 11 12 ...
Page 40: ...HT DV40H 6 10 Figure 6 9 USB SCHEMATIC DIAGRAM BI706 A B C D E F G H 1 2 3 4 5 6 ...
Page 41: ...HT DV40H 6 11 MEMO ...
Page 45: ...HT DV40H 6 15 Figure 6 13 DISPLAY SCHEMATIC DIAGRAM 2 2 7 8 9 10 11 12 ...
Page 47: ...HT DV40H 6 17 MEMO ...
Page 49: ...HT DV40H 6 19 Figure 6 16 DVD SCHEMATIC DIAGRAM 2 8 7 8 9 10 11 12 ...
Page 52: ...HT DV40H 6 22 Figure 6 19 DVD SCHEMATIC DIAGRAM 5 8 7 8 9 10 11 12 ...
Page 54: ...HT DV40H 6 24 Figure 6 21 DVD SCHEMATIC DIAGRAM 7 8 CD SIGNAL A B C D E F G H 1 2 3 4 5 6 ...
Page 67: ...HT DV40H 6 37 Figure 6 34 WIRING SIDE OF POWER PWB BOTTOM VIEW 2 2 7 8 9 10 11 12 ...
Page 71: ...HT DV40H 6 41 Figure 6 38 WIRING SIDE OF DISPLAY PWB BOTTOM VIEW 2 2 7 8 9 10 11 12 ...
