HT-DV40H
8 – 19
GPIO/M_DD[18]
169
Input/Output
GPIO[45] or SDRAM data bus bit 18
GPIO/M_DD[17]
171
Input/Output
GPIO[46] or SDRAM data bus bit 17
Symbol
Pin #
Input/Output
Description
Priority selection
Function
Dir
hw_cfg_chg[5]=1’b1
SDRAM data bus [18]
Input/Output
gpio_first[2][13] = 1
GPIO[45]
Input/Output
sft_cfg13[14:12] = 3'b001
AT_D[6]
Input/Output
sft_cfg13[14:12] = 3'b100
AT_D[6]
Input/Output
{sft_cfg20[0],sft_cfg7[5:4]} =
3'b001
656_DATA[5]
Output
{sft_cfg20[1],sft_cfg19[5:4]} =
3'b001
HD_DATA[5]
Output
{sft_cfg20[2],sft_cfg14[7:6]}=
3'b001
SRGB_DATA[5]
Output
sft_cfg11[8:6] = 3'b011
TS_DATA[1]
Input/Output
sft_cfg0[13:12] = 1
TV_LCD_B[3]
Output
sfg_cfg15[15:12] = 4'b0100
FM_GPIOB[7]
Input/Output
sfg_cfg16[15:12] = 4'b0001
FM_GPIOB[12]
Input/Output
sfg_cfg16[15:12] = 4'b0110
FM_GPIOB[15]
Input/Output
sfg_cfg17[3:0] = 4'b0101
FM_GPIOB[17]
Input/Output
sfg_cfg18[3:0] = 4'b1000
FM_GPIOB[37]
Input/Output
sfg_cfg18[3:0] = 4'b1001
FM_GPIOB[39]
Input/Output
(other)
GPIO[45] (default)
Input/Output
Priority selection
Function
Dir
hw_cfg_chg[5]=1’b1
SDRAM data bus [17]
Input/Output
gpio_first[2][14] = 1
GPIO[46]
Input/Output
sft_cfg13[14:12] = 3'b001
AT_D[8]
Input/Output
sft_cfg13[14:12] = 3'b100
AT_D[9]
Input/Output
{sft_cfg20[0],sft_cfg7[5:4]} =
3'b001
656_DATA[6]
Output
{sft_cfg20[1],sft_cfg19[5:4]} =
3'b001
HD_DATA[6]
Output
{sft_cfg20[2],sft_cfg14[7:6]}=
3'b001
SRGB_DATA[6]
Output
sft_cfg11[8:6] = 3'b011
TS_DATA[2]
Input/Output
sft_cfg0[13:12] = 1
TV_LCD_B[4]
Output
sfg_cfg16[3:0] = 4'b0100
FM_GPIOB[8]
Input/Output
sfg_cfg16[11:8] = 4'b0001
FM_GPIOB[11]
Input/Output
sfg_cfg16[15:12] = 4'b0110
FM_GPIOB[14]
Input/Output
sfg_cfg17[3:0] = 4'b0101
FM_GPIOB[18]
Input/Output
sfg_cfg18[3:0] = 4'b1000
FM_GPIOB[36]
Input/Output
sfg_cfg18[3:0] = 4'b1001
FM_GPIOB[40]
Input/Output
(other)
GPIO[46] (default)
Input/Output
Summary of Contents for HT-DV40H
Page 13: ...HT DV40H 2 6 MEMO ...
Page 15: ...HT DV40H 4 2 IC701 IXA161AW00 PR PB Y S01 Figure 4 2 MAIN BLOCK DIAGRAM 2 2 ...
Page 19: ...HT DV40H 4 6 Figure 4 6 POWER BLOCK DIAGRAM 2 2 ...
Page 30: ...HT DV40H 5 11 MEMO ...
Page 34: ...HT DV40H 6 4 Figure 6 3 MAIN SCHEMATIC DIAGRAM 3 8 TO SUBWOOFER PWB D BI402 13 14 15 16 17 18 ...
Page 35: ...HT DV40H 6 5 Figure 6 4 MAIN SCHEMATIC DIAGRAM 4 8 MIC_IN A B C D E F G H 1 2 3 4 5 6 ...
Page 36: ...HT DV40H 6 6 Figure 6 5 MAIN SCHEMATIC DIAGRAM 5 8 AZ4558CME JP826 7 8 9 10 11 12 ...
Page 38: ...HT DV40H 6 8 Figure 6 7 MAIN SCHEMATIC DIAGRAM 7 8 AUDIO SIGNAL A B C D E F G H 1 2 3 4 5 6 ...
Page 39: ...HT DV40H 6 9 Figure 6 8 MAIN SCHEMATIC DIAGRAM 8 8 SPEAKER TERMINAL 7 8 9 10 11 12 ...
Page 40: ...HT DV40H 6 10 Figure 6 9 USB SCHEMATIC DIAGRAM BI706 A B C D E F G H 1 2 3 4 5 6 ...
Page 41: ...HT DV40H 6 11 MEMO ...
Page 45: ...HT DV40H 6 15 Figure 6 13 DISPLAY SCHEMATIC DIAGRAM 2 2 7 8 9 10 11 12 ...
Page 47: ...HT DV40H 6 17 MEMO ...
Page 49: ...HT DV40H 6 19 Figure 6 16 DVD SCHEMATIC DIAGRAM 2 8 7 8 9 10 11 12 ...
Page 52: ...HT DV40H 6 22 Figure 6 19 DVD SCHEMATIC DIAGRAM 5 8 7 8 9 10 11 12 ...
Page 54: ...HT DV40H 6 24 Figure 6 21 DVD SCHEMATIC DIAGRAM 7 8 CD SIGNAL A B C D E F G H 1 2 3 4 5 6 ...
Page 67: ...HT DV40H 6 37 Figure 6 34 WIRING SIDE OF POWER PWB BOTTOM VIEW 2 2 7 8 9 10 11 12 ...
Page 71: ...HT DV40H 6 41 Figure 6 38 WIRING SIDE OF DISPLAY PWB BOTTOM VIEW 2 2 7 8 9 10 11 12 ...
