Sharp FO-DC600, Service Manual, Page: 64 / 150

FO-DC600U
Fig. 2 HD6417706F133 BLOCK DIAGRAM
MMU
CPU
SCI
TMU
RTC
SCIF
ADC
DAC
UBC
AUD
BSC
DMAC
CMT
I/O PORT
EXTERNAL BUS
INTERFACE
Legend:
ADC:
AUD:
BSC:
CACHE:
CCN:
CMT:
CPG/WDT:
CPU:
DAC:
A/D converter
Advanced user debugger
Bus state controller
Cache memory
Cache memory controller
Compare match timer
Clock pulse generator/watchdog timer
Central processing unit
D/A converter
DMAC:
H-UDI:
INTC:
MMU:
RTC:
SCI:
SCIF:
TLB:
TMU:
UBC: Direct memory access controller
Hitachi user-debugging interface
Interrupt controller
Memory management unit
Realtime clock
Serial communication interface (with smart card interface)
Serial communication interface (with FIFO)
Address translation buffer
Timer unit
User break controller
TLB
CCN
L BUS
PERIPHERAL BUS 1
PERIPHERAL BUS 2
CACHE
H-UDI
INTC
CPG/WDT
BRIDGE
I BUS 1
I BUS 2
5 – 2