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FO-DC600U

2. Description of each block

(1) Main control block

This block consists of 32 bit RISC microcomputer HD6417706F133 (main
component), flash ROM, 128 Mb SDRAM, Main ASIC, Sub ASIC, etc.
Each device is controlled either by the microcomputer directly or via
Main ASIC.

1) HD6417706F133 (IC24): pin-176, QFP (main CPU)

This is a microcomputer with a core of 32 bit RISC (Reduced Instruc-
tions Set Computer) CPU, which periphery functions are integrated into.
This device is equipped with the following function. The clock inputs
33.1776 MHz from outside and operates at 4-times frequency (approx.
133 MHz) internally.

Feature

· Original Hitachi SuperH architecture
· Object code level compatible with SH-1, SH-2 and SH-3
· 32-bit RISC-type instruction set

— Instruction length: 16-bit fixed length

— Improved code efficiency

— Load-store architecture

— Delayed branch instructions

— Instruction set oriented for C language

· Five-stage pipeline
· Instruction execution time: one instruction/cycle for basic instructions
· General-register: Sixteen 32-bit general registers
· Control-register: Eight 32-bit control registers
· System-register: Four 32-bit system registers
· 32-bit internal data bus
· Logical address space: 4 Gbytes
· Space indentifier ASID: 8 bits, 256 logical address space
· Abundant Peripheral Functions

— Memory Management Unit (MMU)

— User Break Controller (UBC)

— Bus state Controller (BSC)

— Direct Memory Access Controller (DMAC)

— Clock Pulse Generator (CPG)

— Watchdog Timer (WDT)

— Timer Unit (TMU)

— Realtime Clock (RTC)

— Serial Communication Interface (SCI)

— Smartcard Interface

— Serial Communication Interface with FIFO (SCIF)

— 10-bit A/D converter (ADC)

— 8-bit D/A converter (DAC)

— Hitachi User Debugging Interface (H-UDI)

— Advanced User Debugger (AUD)

2) LH28F320BFHE-PBTLZA (IC12): pin-48, TSOP (32 Mb

FLASH MEMORY)

This is a flash memory writing program and is also used for the registra-
tion data, such as telephone directory.
32 Mb area is divided into 2 for every 16 Mb; the lower-order and higher-
order address sides are used for the program and for the registration
data, respectively.

3) MT48LC8M16A2TG or W981216BH (IC25): pin-54, TSOP

(128 Mb SDRAM)

The program stored in the flash memory (IC12) mentioned in the above
item 2) is downloaded to this SDRAM and used as a program execution
memory. It is also used as various work memories and communication
buffers. The devices manufactured by 2 enterprises are acknowledged.
(Former model No.: manufactured by WINBOND, later model No.: manu-
factured by MICRON)

CHAPTER 5. CIRCUIT DESCRIPTION

[1] Circuit description

1. General description

In this machine, the facsimile control block except the printer control is
mainly composed of the units shown in Fig. 1.

2. PWB configuration

Fig. 1

1) Control PWB

The control PWB controls all the other operations except the printing
operation of the printer.

2) CIS unit

CIS UNIT converts the image of the sending or copying draft into the
photoelectric signals and transmits the signals to the control PWB.

3) LIU PWB

The LIU PWB controls the I/F telephone function of the circuit with the
control signals from the control PWB.