Sharp AQUOS LC-42AD5E, Service Manual

Page: 76 / 144

LC-42AD5E/RU/S
5 – 19
17 CAS I Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
16 WE I Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
15 LDQM I Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
39 UDQM I
2 DQ0 I/O Data inputs/outputs are multiplexed on the same pins.
4 DQ1 I/O
5 DQ2 I/O
7 DQ3 I/O
8 DQ4 I/O
10 DQ5 I/O
11 DQ6 I/O
13 DQ7 I/O
42 DQ8 I/O
44 DQ9 I/O
45 DQ10 I/O
47 DQ11 I/O
48 DQ12 I/O
50 DQ13 I/O
51 DQ14 I/O
53 DQ15 I/O
1, 14, 27 VDD — Power for the input buffers and the core logic.
28, 41, 54 VSS — Ground for the input buffers and the core logic.
3, 9, 43, 49 VDDQ — Isolated power supply for the output buffers to provide improved noise immunity.
6, 12, 46, 52 VSSQ — Isolated ground for the output buffers to provide improved noise immunity.
40 N.C/RFU — This pin is recommended to be left No Connection on the device.
36 N.C —
Pin No. Pin Name I/O Pin Function