No.11S098-03
31
STC-GE33OX/GEC33OX
Users guide Rev. 1.03
3.4.4 Recommend the image data handle between the Sentech FPGA and the user configurable FPGA
Recommend to make the image processing with synchronize CLKIN when make the image processing in the
user configurable FPGA.
Recommend to set timing restriction for secure the timing margin of CLKIN and the image data (DIN, DOUT,
LVALIN, LVALOUT, FVALIN, FVALOUT) between the Sentech FPGA and the user configurable FPGA.
Please check the sample code for details.
3.4.5 Copy guard function
The user configurable FPGA (XILINX: XC3SD1800A) supports
“Device DNA security function” for the FPGA
design protection.
The user configurable FPGA has 57 bit unique ID. This ID can use for the security key.
Please check the XILINX application note: WP266.
3.4.6 Schematics of the user configurable FPGA (XILINX)
Please check
Schematics of user configurable FPGA (XILINX)
.
Image
processing 1
Image
processing 2
Image
processing 3
User configurable FPGA
The image data (DIN, LVALIN, FVALIN)
from the Sentech FPGA is
Flip-Flop output with the rising edge
of CLKIN after input image data
The image data (DIN, LALIN, FVALIN)
at each image processing is
Flip-Flop output with the rising edge
of CLKIN
When select the image data,
the image data (DIN, LVALIN, FVALIN)
is Flip-Flop output with the rising edge
of CLKIN after select the image data
The image data (DOUT, LVALOUT, FVALOUT)
to the Sentech FPGA is Flip-Flop output with the
rising edge of CLKIN
Output signals to
Sentech FPGA
DOUT [11:0]
LVALOUT
FVALOUT
Input signals from
Sentech FPGA
DIN
[11:0]
LVALIN
FVALIN
CLKIN
Fig. 8 Recommend image data handle
