No.11S098-03
28
STC-GE33OX/GEC33OX
Users guide Rev. 1.03
3.3.3 Connection between the user configurable FPGA (XILINX) and the EEPROM
(Note) Signal directions indicated as inputs and outputs
are referencing to the user FPGA. “Input” means a
signal from the DDR2 to the user EEPROM
and “output” means from the user FPGA to EEPROM.
Please sets Float, Pull-up or Pull-down for unused input signal of the user configurable FPGA.
Please sets Pull-up or Pull-down, or sets [H] or [L] with RTL code, for unused output signal of the user
configurable FPGA.
No
Signal Name
Direction Discription
Pin No. of User FPGA
1 ROM_512KBIT_CLK
output
Serial Clock for ROM
U20
2 ROM_512KBIT_nS
output
Chip Select for ROM
T17
3 ROM_512KBIT_DATA output
Serial Data input for ROM
T20
4 ROM_512KBIT_Q
input
Serial Data output for ROM
T18
5 ROM_512KBIT_nW
output
Write Protect for ROM
R19
(Table-6) Connection between the user configurable FPGA (XILINX) and the EEPROM